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Design Compiler
This course covers the ASIC synthesis flow using Design Compiler Topographical / Graphical -- from reading in an RTL design (Verilog, SystemVerilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries and physical data, constrain a complex design for timing and floorplan, apply synthesis techniques using Ultra, compile to achieve timing closure and an acceptable congestion, analyze the synthesis results for timing and congestion, and generate output data that works with downstream layout tools.
You will verify the logic equivalence of synthesis transformations (such as Datapath optimizations and Register Retiming) to that of an RTL design using Formality. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 5-page Job Aid, which you can refer to back at work.
Objectives
At the end of this workshop the student should be able to:
Create a setup file to specify the libraries and physical data
Read in a hierarchical design
Constrain a complex design for timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew
Constrain multiple (generated) clocks considering Signal integrity analysis
Execute the recommended synthesis techniques to achieve timing closure
Analyze and Improve global route congestion that is layer aware
Perform test-ready synthesis
Verify the logic equivalence of a synthesized netlist compared to an RTL design
Write DC-Tcl scripts to constrain designs, and run synthesis
Generate and interpret timing, constraint, and other debugging reports
Understand the effect that RTL coding style can have on synthesis results
Generate output data (netlist, constraints, scan-def, coarse placement) that is needed to implement layout (place and route)
Audience Profile
ASIC digital designers who are going to use Design Compiler, to synthesize Verilog/SystemVerilog or VHDL RTL designs to generate gate-level netlists enabling timing closure and predictable congestion
Prerequisites
To benefit the most from the material presented in this workshop, students should:
Understand the functionality of digital sequential and combinational logic
Have familiarity with UNIX and a UNIX text editor of your choice
No prior Design Compiler knowledge or experience is needed.
Course Outline
Introduction to Synthesis
Design and Technology Data
Design and Library Objects
Timing Constraints
Environmental Attributes
Synthesis Optimization Techniques
Timing Analysis
Additional Constraint Options
Multiple Clocks and Timing Exceptions
DC-Graphical Features
Post-Synthesis Output Data
Conclusion
Synopsys Tools Used
Design Compiler 2015.06-SP5
Formality 2015.06-SP5君，已阅读到文档的结尾了呢~~
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