Altium Designer入门设计_图文_百度文库
两大类热门资源免费畅读
续费一年阅读会员，立省24元！
Altium Designer入门设计
上传于||文档简介
&&A​l​t​i​u​m​ ​D​e​s​i​g​n​e​r
阅读已结束，如果下载本文需要使用
想免费下载本文？
下载文档到电脑，查找使用更方便
还剩18页未读，继续阅读
你可能喜欢面向装配模型的协同浏览、批注、查询技术研究 ...
扫扫二维码，随身浏览文档
手机或平板扫扫即可继续访问
面向装配模型的协同浏览、批注、查询技术研究
举报该文档为侵权文档。
举报该文档含有违规或不良信息。
反馈该文档无法正常浏览。
举报该文档为重复文档。
推荐理由：
将文档分享至：
分享完整地址
文档地址：
粘贴到BBS或博客
flash地址：
支持嵌入FLASH地址的网站使用
html代码：
&embed src='/DocinViewer-4.swf' width='100%' height='600' type=application/x-shockwave-flash ALLOWFULLSCREEN='true' ALLOWSCRIPTACCESS='always'&&/embed&
450px*300px480px*400px650px*490px
支持嵌入HTML代码的网站使用
您的内容已经提交成功
您所提交的内容需要审核后才能发布，请您等待！
3秒自动关闭窗口libraries of schematic symbols and layout footprints
libraries of schematic symbols and layout footprints
see also Making your own symbols , and making your own footprints
Vounteers have donated footprints at
Brian Guralnick
has generously donated
a library with both "schematic components" and "PCB footprints" ("land patterns")
has moved elsewhere ?] and
"all schematic discrete components are optimized for the schematic capture
display. They are super compact. The pcb foot prints are also space optimized."
``Except for double diodes, discrete component pinouts are B,S,E, G,S,D,
A,K instead of pin numbers for matching footprints within your own footprint
libraries.''
Protel keeps putting updated parts libraries on its web site: Protel Libraries
/library/ */ and
.au/library/index.html */ and
a free library of footprints and symbols (which they call ``decals''):
(is this compatible with Protel ?)
Q: What's the quickest way to print a page that lists *all* the footprints
of a pcb library ? Looking at a page full of footprints at once is much faster
than scrolling through the library looking at one at a time. (Especially
with several pcb libraries full of parts).
A: "Geoff Harland"
PM writes: (lightly edited by the FAQ maintainer):
Create a new blank Pcb file.
Open the pcb footprint library file (``.lib'') you're interested in, and
look at one of the footprints.
With the Design Manager panel on, select the "Browse PCBLib" Tab while you
have the Pcb Library file concerned currently selected.
Using the left mouse button, click on the *first* footprint listed in the
Design Manager panel.
While holding a Shift key down, (left mouse button) click on the *last* footprint
listed in the Design Manager panel. *All* of the footprints listed in the
Design Manager panel should now be in a highlighted state.
While the cusor is located over the area listing these footprints, right-mouse
click, then select "Copy" from the resulting popup menu.
Switch to the (blank) Pcb file, then do ``Edit | Paste'' and click in the
PCB area. One copy of each of the footprints will then be pasted into the
Pcb file. Now all the components are in a pile where you clicked.
Select the components (perhaps with "Select | All").
From the Component Placement toolbar, select the ``Arrange selected components
within defined area'' icon. (If you let the mouse pointer rest on any icon
for a couple of seconds, a short line of text pops up explaining that icon.)
Click in the PCB area 2 or more times to space out the components.
[optional] Add a string to the Drill Drawing layer, with a caption of .LEGEND
(this is a Special String), and preferably place this in the lower left hand
corner of the Pcb file.
[optional] Run a process to set the Comment field of each component within
a Pcb file equal to its Footprint (string). Geoff Harland wrote a PcbAddon
Server to do this.
If you have Protel 99 SE sp 6, use
If you have Protel 99 SE sp 5, use
There's several different things you can do at this point.
You can now produce a printout (``File | Print...'').
If you print just the Drill Drawing layer, the printout will index and count
the usage of each hole size used.
You can now generate a report (``Reports | Board information...'')
You can use the CAM manager to produce Drill files from the PWB file. The
Drill Report file will list the number of hole sizes used, and the number
of times each size is used.
Q: Which footprint should I use ?
A: Unlike through-hole components, there is no One True Footprint for a SMT
(a) If a dot of glue is placed under each component, the pads can be very
small and the components can be packed very close together -- the glue holds
them in the correct location during reflow.
(b) If you space components out a little more and use a little larger footprint,
components on the top side don't need glue -- they will "auto-align" from
the solder surface tension during reflow. (For example, the "SOT-23" footprint
in the "Advpcb.ddb" library).
(c) If you wave-solder components together, you need an even larger SMT footprint
to reach out and catch the solder and pull it into the pins. (For example,
the "SOT23" in the "Discrete IPC.ddb" library). Also, you need something
called a "solder thief".
My understanding is that IPC footprints are (were ?) optimized for (c) wave
soldering, so many people use smaller footprints that work fine for their
process (a) or (b).
There is a (free) online land pad calculator from IPC,
Bugs in the Protel footprint library (Have these been fixed already ?)
Protel's General IC.ddb has footprints that look correct except for one little
detail: ZIP-7H ZIP-11H ZIP-15H TO-220-3S TO-220-5S TO-220-7S would all probably
work fine for a little while. But they would be better if the footprint included
one more pad under the ``flag'', under the main body of the component. That
flag is connected to the middle pin of the component. 3 reasons for the flag
pad: (a) a flag pad makes absolutely sure I don't route any traces underneath
that metal flag. Maybe I'm paranoid, but I don't trust that green solder
mask to insulate signal traces from that metal flag. (b) Thermal path is
much better with flag soldered to a nice large copper pad, than forcing heat
through solder mask or pins. (c) All the manufacturer data sheets show that
flag pad in the recommended land pattern. (I'm looking at National Semiconductor
right now.)
Several of the footprints Protel supplies in their "SQFP & QFP Square
IPC.ddb/SQFP & QFP Square 2 IPC.lib" library (as of 2000-04 ?) are not
merely nonstandard, but (IMHO) incorrect. In particular, SQFP24x24-176(N)
SQFP24x24-176(T) SQFP24x24-185(N) SQFP24x24-185(T) ( possibly all the components
in this library ) have pads with a much-too-narrow gap between them.
The "SOT-25" footprint in "PCB Footprints.lib" is physically the same as
the "SOT-23-5" footprint used by Maxim for lots of interesting stuff, but
watch out -- the pins are numbered differently.
"In Protels new ISO9001 Newport.ddb library the PCB footprint sip-p4/a6 is
mirrored. I guess they missed the note on the data sheet that said bottom
view." -- Vince Vlach
the DIN-96 type C connector found in the PROTEL library (GENERIC
FOOTPRINTS/MISCELLANEOUS.LIB). The distance between screwholes in this footprint
is 3.500", but it should be 90.0mm (~3.54"). -- Hans
03:56:02 PM
(schematic library design tips for making new symbols.)
If you want a symbol that's not already in the
you must make it yourself in your own library.
When designing a new schematic symbol, Ian Wilson says: "don't use hidden
pins ... ever. The are not logical or intuitive and new users consistently
have problems with them."
There seem to be 2 kinds of schematic symbols:
pseudo-layout: the symbol on the schematic has roughtly the same shape
(rectangular or square) as the real, physical component. Each and every the
pin on the real, physical component is shown on the symbol in roughly the
same relative position. [Is there a standard way to indicate (on paper) which
pins are input and which pins are output on a pseudo-layout style schematic
symbol ???]
functional: a symbol has inputs on the left (and sometimes top and bottom),
outputs on the right. The power symbol for a component has positive power
on top, ground and negative power on bottom. Common for discrete gates (AND,
NAND, NOR, etc.) and op amps. Some libraries break a quad package into 5
symbols, a "power" part and 4 identical "function" parts. You must place
*all* the parts of a real component somewhere on the schematic. [enhancement:
someday ERC ought to check that every part of the real component is somewhere
on the schematic].
When making a new shematic symbols, it helps to
reduce pin length to 10
make sure the "active end" of the pin is on-grid
double-click each pin and set the electrical type appropriately. (This helps
ERC). (Some people don't use the "power" electrical type, setting all power
input pins to "input" instead. This catches the error of having lots of chips
trying to pull power from +5V, but neglecting to actually supply +5V to the
If it's a diode, use the pin "numbers" A and K rather than 1 and 2.
If it's a transistor, use the pin "numbers" C B E or D G S rather than 1,
If it's a polarized capacitor, make the "+" side pin 1 with a straight plate,
the "-" side pin 2 with a curved plate.
If it's a quad package, think about breaking it into 5 symbols: a "power"
part and 4 identical "function" parts.
(The pin "numbers" on the schematic symbol must match up with corresponding
"numbers" on the PWB footprint. The pin "names" on the schematic are just
for documentation.)
Bug: The "update schematic" button really ought to (1) take the version of
the part in memory (which you have just edited) and save it to disk, *then*
(2) use the version on disk to update open schematics.
But at the moment, it only does step (2).
Workaround: Always ``press the "file save" button before you press the "update
schematic" button.'' -- "Graeme Zimmer"
05:38:42 PM
Q: How do I copy a schematic symbol from some other library to my own personal
schematic symbol library ?
A: After I right-click on the name of the component (in the left pane of
the symbol editor), I choose "copy". No more clicks needed. Then I switch
to my own personal libraries, right-click in that left pane, and choose "paste".
Don't have to click again here either. In the schematic symbol editor, there's
no way to do that from the menu options -- you *must* do it with the right-click
thing. I wish for a ``Edit | Copy Component'' and a ``Edit | Paste Component''.
Unfortunately, the ``Tools | Copy Component...'' does *not* do the right
thing. Then rename it.
If the footprint you want isn't already in the
, then you'll have
to make your own footprint.
If you're lucky, you don't need to create your own footprint library. Most
boards can be built out of components that fit the standard footprint libraries.
for footprint libary
If you create a new library, please please please embed a description of
the library -- your name, email address, web page, the date it was created,
the date of this revision, etc. Create an extra dummy component named "__about"
with a bunch of "top overlay" silkscreen strings that list this text information
("metadata"). If you use the ".ddb" format, put a simple text file "readme.txt"
in each ".ddb" database with this information.
making a new footprint, it helps to
If it's a diode, use the pin "numbers" A and K rather than 1 and 2.
If it's a transistor, use the pin "numbers" C B E or D G S rather than 1,
If it's a polarized capacitor, make the "+" side pin 1 the "-" side pin 2.
[Or would it be better to use pin ``numbers'' A and K ?]
Make a bar, or plus, or some other polarity indicator.
Gotcha: the "bar" on capacitors indicates the A +anode, while the "bar" on
diodes indicates the K -cathode.
Thru-hole components traditionally have a square pad on pin 1, and round
pads on all other pins.
Exception: Only if the footprint is so assymetrical that it's impossible
to put the component on backwards (for example, the sot-23), or if it really
doesn't matter if you put in in backwards (
non-polarized capacitors) then you don't need to indicate polarity.
If it's a connector, silkscreen a ``1'' next to pin 1.
``PLCC’s, PQFP’s, or any other high density IC’s shall have
their corner pin numbers silkscreened adjacent to the appropriate pad. Large
components (over 120 pins) shall have additional hatch marks at every 10th
pad. BGA’s and PGA’s shall have their row / column numbers silkscreened
along side of them.'' --
If it's surface mount, make the "pick point" (location 0,0) at the center
of the component. (Select | All, then drag it over). ``I like to use centroid
reference because it makes it easy to rotate parts in place, and also to
line them up after some of them have been rotated.'' -- "Abd ul-Rahman Lomax"
05:35:44 PM
Q: How do I copy a footprint from some other footprint library to my own
personal footprint library ?
A: I right-click on the name of the component (in the left pane of the footprint
editor), and choose "copy". No more clicks needed. Then I switch to my own
personal libraries, right-click in that left pane, and choose "paste". Then
rename it. In the footprint editor, I think this is the same as using ``Edit
| Copy Component'', then flipping to my own library .ddb and doing ``Edit
| Paste Component''.
Bug: The footprint I just pasted has the pick point (location 0,0 in the
footprint editor) is centered on pin 1, no matter where it was on the original
footprint. Manually fix it (see
``First thing you do after "Tools/New Component", is "Tools/Rename Component".''
-- Peter Bennett. ``Using the same name for 2 different footprints is asking
for trouble.'' -- David Cary.
footprint design tips: [FIXME: should I move "component footprint design"
to its own page, http://massmind.org/techref/app/pwb_design_flow.htm#footprint
http://massmind.org/techref/pwb_layers.htm
http://massmind.org/techref/app/pwb_libraries.htm ?]
Q: Does anyone out there wave solder 0603 components and can you provide
a land design ... ? -- Mark Yankee
A: Rich Schutz
01:50:30 PM
We ... Design the lands per IPC then add the extra pad. Do not change the
of the pads. You want the extra pad on the ends to prevent shadowing.
We add .020" to the outside pad edge for all chip resistors
add .030" to ... Chip capacitors.
From: rlamoreaux
To: "Protel EDA Forum"
Subject: Re: [PEDA] SMT Land Pattern Design
I have generally used a combined approach which made since with older
versions of Protel, and is a little more difficult with newer.
Older versions of Protel had two spacings, one for large components and the
other for small. I made the small components like 0805 parts so the
silkscreen would overlap and form one 10 mil line at the proper
spacing, and large components had a spacing from their outmost pad or
silkscreen. This worked good for me.
This was useful since it is
hard to draw an outline for a small part unless it is on the edge of
the placement area, and some large parts can look strange with a lot
of silkscreen around them.
With the current version of Protel I will create a class for small
components and a class for large to do the same thing. Then I can
create rules to set the proper spacing for all the different types of
Common footprints people design:
company logo
Most people put their company logo into their database:
From: HxEngr
12:11:48 PM
To: Multiple recipients of list proteledausers
Subject: Re: [PROTEL EDA USERS]:
Place Graphics into PCB
In a message dated 8/31/00 12:55:49 PM Eastern Daylight Time,
& Is there a way to place Graphics like a Company Logo into a PCB Data
One way that I've used is to build a footprint which contains the appropriate
shapes, text, or whatever, either in the copper layers or the silkscreen. I
even sometimes place a dummy "testpoint" part which calls for that footprint,
in an obscure corner of the schematic so it doesn't get removed if I fully
update the netlist. Biggest drawbag is that you can't handily scale the logo
this way, so you might need to make several of different sizes, depending
upon your needs.
Steve Hendrix
Abd ul-Rahman Lomax
05:26:17 PM
said [witty remarks ruthlessly snipped and other edits by the FAQ maintainer]:
At 08:11 AM 8/31/00 +0000, Ron Tupa wrote:
&Is there a way to place Graphics like a Company Logo into a PCB Data
There are two utilities. One of them is free, convert.zip,
converts BMP to Protel
Connect to . Visit abdlomax. Activate the link under Storage,
Convert.zip. Check the box beside Convert.zip and push the Download button.
Unfortunately, I just checked and idrive is not allowing guest access,
temporarily, they claim.
So I'm uploading it also to the filespace for
protel-. That filespace is publically accessible, you
don't have to be a subscriber to protel-.
(But I do recommend that all Protel users s it's a
backup list for this (techserv) list, which is occasionally down. There are
about fifty subscribers to the backu please do not
post to protel-users except in an emergency, unless the association decides
to do something else with protel-users.)
Convert.zip contains a utility to convert BMP files to Protel format.
The other program is:
&PCBLOGO costs $15(US) and is available from Henry Velthuizen,
&&hfav at paradise.net.nz&, 104 Upper Fitzherbert Road, Wainuiomata, New Zealand.
I'll also remind users that there is an ad list for Protel-related products
and services: protel-users-. Like all the egroups lists,
that list has an archive, so postings to the list will remain accessible
for a long time.
Note that there are not very many subscribers to protel-users-ads, but the
egroups archives are indexed by major search engines and the
archives are publically accessible. So an ad there may reach an audience
far beyond the subscription base.
For an example, search on
(my favorite search engine) for
"Protel resale" and you will find pages from the mailing list
protel-users-. Following up that search could save a
Protel buyer upwards of $3000....
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
Brian Guralnick has written:
PicToGBR.zip - 3kb -& source & instructions on how to convert a 256
shade gray image to Gerber.
pictogerberexample.zip - 182kb -& 3 images already converted into Gerber,
both in circle mode & square mode. Select 'TopOverlay layer', then import.
For large fine-pitch ICs, some people put a fiducial centered "underneath"
the IC while others put 2 fiducials at opposite corners of the IC [what
difference does it make ?]. If the IC land pattern in the footprint library
already includes this fiducial, then it makes it easier at board layout time
to place the component and move it around -- the board designer doesn't have
to go back and manually re-center a fiducial under that IC.
has layout tips for BGA packages. ``Non solder mask defined land patterns
or land defined land patterns are recommended for CS and FG. Solder mask
defined land patterns are recommended for BG.''
pre-routed BGA
If you use BGAs, you might want to use a footprint that includes traces
"pre-routed" from the balls to the perimeter of the part. (Unfortunately,
there is a bug in the 99SE auto-router -- the auto-router sometimes rips
up those pre-routed traces. Work-around: change the footprint to any other
arbitrary footprint, then change back to the correct footprint to re-load
that footprint from the library. Then
"Design | Netlist Manager | Menu | Update Free Primitives From Component Pads"
to get those pre-routed traces connected to the correct net.
Q1a: How do I make a custom pad shape ? (I need something other than the
simple pads shapes built-in to Protel: "circle", "rectangle", "oval", and
"octagon")
A1: Build the custom pad shape out of several overlapping pads on the top
layer (and optionally a through-hole pad on the multilayer). Assign them
all the same reference designator.
A2: For even more flexibility, build the custom pad shape out of overlapping
fills on *both* the top paste mask layer *and* the top copper layer. Place
a small simple pad touching those fills. (Either a surface-mount pad on the
top layer or through-hole pad on the multilayer).
Q1b: I tried that, but when I placed that footprint on my PWB, it lights
up bright green with lots of DRC errors.
A1b: run "Design | Netlist Manager | Menu | Update Free Primitives From Component
Pads" and run another DRC check.
One under-appreciated ``component'' is the ``virtual short'', also known
as a ``star point'' which can be used as a ``star ground''. (However, many
people point out that . )
shorting jumper (virtual short)
Q: ``Isn't there some way to put ... a trace on the board that is ignored
for DRC checks ? ... Also, I want to put jumpers on my board that are shorted
on the PCB. That means that to use the jumper I have to cut the trace on
the PCB. How do I do this? It is the same type of question. '' -- Russell
Since you want the 2 nets to connect at one and only one place, symbolize
that place on your schematic with a 0 Ohm resistor symbol or ``Create a schematic
symbol, call it TIE, that looks like a short bar with a pin at each end.
When placing the symbol on the schematic, you will be able to preserve your
individual net names.'' -- John Lemburg
on . Then give that component the special "TIE" footprint.
Abd ul-Rahman Lomax
01:21:58 PM
a shorting component that is open to DRC and shorted in the actual copper.
The basic idea is to use a very small distance between [``surface mount'']
pads or fills (pads are better because they can be named). In the schematic
is an ordinary jumper, between, for example, GND and GNDA. The pads have
a dimension in the contact direction which is, say, .002 mil (yes, 2 microinches)
short of contact, and a Design Rule is created to allow those two pads to
be so close without generating a clearance error. Once such a component is
made, it can be used for any PCB. If one forgets to make the Design Rule,
one gets reminded. ...
So one has control *from the schematic* over
a single-point short -- which is what is ordinarily needed -- and additional
shorts will be reported as DRC errors (unless, of course, one has placed
more than one short), and the position of the short is clearly and easily
controlled. It's easy to implement star grounds with this, by having several
of these shorting components side-by-side. (These are non-BOM components....)
For prototype work, an ordinary jumper [footprint] can be used instead of
the shorting component, allowing the replacement of the short by an inductor
the jumper is then replaced with the shorting footprint when
the production gerbers are created.
Geoff Harland adds,
Doing things this way means that the implementation is *also* documented
by the schematic file, and it is not necessary to tolerate DRC errors (in
the PCB file), or to add any shorting tracks *after* running a DRC check
(and before producing Gerber files).
To prevent [the TIE component] from being imaged on the Gerber file for the
Paste Mask layer, set the Paste Mask expansion value to a sufficiently negative
value so as to mask these pads on this layer. (This can be done with a Design
Rule, or from the 'Pad' dialog box invoked after clicking on each of the
pads concerned.) And unless you want the copper in the area of these pads
to be exposed on the actual PCB, similarly mask these pads on the Solder
Mask layer as well. (Again, either by defining a Design Rule, or from the
'Pad' dialog box.)
Other people use this PWB footprint:
``Create a PCB shape for TIE that looks like interleaved fingers of trace,
like 4 from one end and 5 from the other, so that the fingers are not
electrically connected when the board is fab'ed. The TIE pattern can be made
large or small -- or very small -- depending on the ground currents. The
TIE PCB shape has two connections -- just like the schematic symbol. ...
Place two TIE patterns, one connecting PS ground to GNDA and the other connecting
PS ground to GNDD, very near the common ground point at the DC-DC converter
on the board, on the back side or non-component side. ...
When you build first article, mask off the TIE patterns so they stay electrically
open. Then when you check for ground integrity and non-pollution of that
ground system, you can be absolutely sure that there are no sneak paths!
Remove the mask from the TIE patterns and apply solder. Now they are connected.
In production, they will always be soldered and thus connected. ... Simply
passing the board through wave soldering does the "short" by wetting the
TIE fingers. ...
Any time you want to verify grounds are really connected at one point, at
PS holy ground, simply solder-suck the TIE pattern or patterns for your test.
Solder them back when you are done.''
-- John Lemburg
Leaving the shorting to the very end of the process, with a gap that will
survive fabrication, could make test easier. ... if the bare board is tested,
the TIE method should detect additional shorts taking place in fabrication
between the grounds, shorts that could serious affe
the virtual short method would not. ... However, for RF components which
are never going to see the wave, a virtual short may be superior. ... Zero-ohm
resistors or jumpers ... require the addition of a component or some additional
operation to implement the short [compared to the virtual short]. If it
considered desireable to have the short easily removed and replaced, I'd
recommend a simple two-pin .100 berg pins can be used, or
a wire can be inserted and soldered or cut or resoldered.
-- Abd ul-Rahman Lomax
See "How can I join two nets together on a Schematic and then on the PCB
without creating an ERC and a DRC violation, respectively?"
) for another work-around.
Both of these methods ("virtual short" real 0 Ohm resistor component)
are used when you want DRC to make sure 2 nets are shorted together at one
and only one place. For example, star grounds, the single-point connection
between AGND and DGND. They can also help remind us to put the termination
resistors at the correct end of a trace. Or connecting only at the 2 "ends"
of a planar transformer.
filter designers seem
to really like the "virtual short" component.
``There are a number of advantages to [placing a zero Ohm resistor]. At prototype
stage you can experiment with the options, such as a direct short between
the two grounds, or a resistor, or an inductor. I commonly see a 10 ohm resistor
used for this purpose. Another advantage is simplicity. You already know
how to do this one. ... It is *much* better to use a zero ohm resistor or
one of the other possibilities I will suggest than to merely short the grounds
on the board. This would completely conceal any need to keep the grounds
isolated (meeting at only a single point) and DRC will not detect such shorts,
which could cause the product to fail, and, even worse, such a failure might
be marginal and only occur under some conditions. If you have a single-point
shorting component, you will not have you won't need
to carefully track down your net's meandering to be sure it is isolated
everywhere except the one point you want. ... make a design rule which will
allow the pads of a specific component to be within .001 mil of each other.
Yes, 1 microinch. Since such a gap (1) won't get plotted since the necessary
plot resolution is unattainable with printed circuit board level photoplotters,
(2) if it were plotted, it would not be fabricated since no fabricator could
do this with pc board materials even if he tried hard, ... Just as with a
zero-ohm resistor, this goes on the schematic and has the appropriate footprint
assigned to it. ... The same concept can be used for such fauna as RF inductors
that are only copper pattern on the board, anything that must be treated
as a component for net list purposes, but which actually shorts, contrary
to the net list. I have not discovered a down side to this procedure. ...
There are also some tricks that can be done with plated-through holes. It
is very easy and fast to drill out the plating in a hole to open a connection
which depends on that plating. Because the hole guides the drill, one is
less likely to slip and damage something else on the board.... ''
-- Abd ul-Rahman Lomax
Another description of the same thing:
-1- I defined a schematic symbol named TIE with 2 (unconnected) pins but
graphically showing clearly the desired connection. -2- I defined a PCB library
foot-print TIE with 2 tracks separated by a ~ 0.00003mm gap -3- I defined
a "Component Class" for TIE -4- I defined a "Clearance Constraint" of 0.00003mm
for Class TIE I just ask to my PCB manufacturer if a 0.00003mm gap will be
under the resolution of his process, and it's 100% the case. I don't have
error with schematic (nets are unconnected) and PCB (no net short-circuit
or clearance violation)
-- Rudolf Schaffer
02:31:43 AM
shorting jumper (real)
Brad Velander
11:20:15 AM
Just for your reference we use the following pattern. We have two triangular
drawn pads separated by a diagonal gap of 10 mils. The triangular pad &
diagonal gap makes the visual presentation of the shorting jumper somewhat
unique and less likely to be confused with other pads or features. There
is no soldermask between the two pads. Finally we use a round circular silkscreen
around the pads.
used to point to
a couple of CAD libraries ... have they moved elsewhere?
Questions:
Alas, I doubt this Hirose connector in the standard libraries. Most likely
you will have to build the footprint yourself, using the "Recommended PCB
mounting pattern" described in the datasheet, adding the "pin 1 indicator"
and other things recommended by
Since Digikey sells this part, the easiest way to get its datasheet is to
look it up on Digikey, find
, and click on "Technical information" and "Datasheet".
Does that answer your question?
" where can i find footprint of
DF12A (3.0)-50DS-0.5V
this is an 50 pin connector from Hirose pdf"
file: /Techref/app/PWB_libraries.htm, 38KB, , updated:
09:42, local time:
&&2016 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Please DO link to this page! &/&&/&&A HREF=&/techref/app/PWB_libraries.htm&& libraries of schematic symbols and layout footprints&/A&
After you find an appropriate page, you are invited to
preformated text
site! (posts will be visible only to you before review)
Just type in the box and press the Post button.
( welcomed, but not the &A tag:
Instead, use the link box to link to another page.
to post directly, become page editors, and be credited for their posts.
0) {this.form.act.selectedIndex=0};"
Link?&Put&it&here:&-1||this.value.indexOf('www')>-1) {this.form.act.selectedIndex=2};alert('Changed post type to \'link\'');">
if&you&want&a&response,
please&enter&your&email&address:&
Attn spammers: All posts are reviewed before being made visible to anyone other than the poster.
Did you find what you needed? From: &&
List host: ,
Site host ,
Top posters @
* Page Editors:
James Newton,
Roman Black of
donates from sales of
* Ashley Roll of
donates from sales of
* Monthly rs:
Gregg Rew.
on-going support is MOST appreciated!
Welcome to !}