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安达发工作笔记（2）
任务: am335x一共有两个usb主机控制器，在天嵌的bsp中，一个配置为usb host ,一个配置为了usb otg。现在需要将otg也配置为host。
实际修改过程非常简单：将.config文件中，将CONFIG_USB_OTG，CONFIG_USB_OTG_WHITELIST，CONFIG_USB_OTG_UTILS这几个宏注释掉，重新编译即可。
修改过程中，大概看了一下usb总线驱动程序。
根据usb设备的插拔，根据串口的打印信息，查到了drivers/usb/core/hub.c
usb_hub_init
&&&&&&& kthread_run(hub_thread, NULL, &khubd&) & && 开启hub_thread线程
&&&&&&&&&&&
hub_thread 线程会阻塞，直到hub_irq中断到来调用kick_khubd来解除阻塞
&&&&&&&&&&&&&&&& hub_events
&&&&&&&&&&&&&&&&&&&&&&&&&&& hub_port_connect_change
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& choose_devnum&&&&& 每一个usb主机控制器，可以支持127个设备，因此这个函数给新接入的设备分配一个设备号(1-127)
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& hub_port_init& 这里串口打印出了 &new high-speed USB device number 6 using&
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& usb_new_device
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& usb_enumerate_device
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& usb_enumerate_device_otg
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
is_targeted& 这里很关键，如果将usb设备插入到了otg中，这里会打印出&device v05e3 p0723 is not supported&,这个函数在otg_whitelist.h。
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& announce_device && 这里打印出&New USB device found, idVendor=05e3,idProduct=0723&
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请教高手：am335x外接一个8位的nand flash（K9F1G08U0D）
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内核版本：linux-3.2.0-chipsee-evm.tar.gz
配置完nand init以后，重启动内核打印如下信息：
3147672 bytes read
## Booting kernel from Legacy Image at
Image Name: Linux-3.2.0
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 3147608 Bytes = 3 MiB
Load Address:
Entry Point:
Verifying Checksum ... OK
Loading Kernel Image ... OK
Starting kernel ...
[ 0.000000] Linux version 3.2.0 (gkhope@ubuntu) (gcc version 4.7.3
(prerelease) (crosstool-NG linaro-1.13.1-4.7-30313 - Linaro GCC 2013.03) ) #1 Mon Mar 3 20:02:42 CST 2014
[ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c53c7d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine: am335xevm
[ 0.000000] Memory policy: ECC disabled, Data cache writeback
[ 0.000000] AM335X ES1.0 (neon )
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048
[ 0.000000] Kernel command line: console=ttyO1, mem=512M root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait rootdelay=1 init=/init ip=off
[ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Memory: 512MB = 512MB total
[ 0.000000] Memory: 3264k available, 11024k reserved, 0K highmem
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
[ 0.000000] vmalloc : 0xe0800000 - 0xff000000 ( 488 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
[ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB)
[ 0.000000] .text : 0xc0008000 - 0xc16 kB)
[ 0.000000] .init : 0xc0584000 - 0xc05c1000 ( 244 kB)
[ 0.000000] .data : 0xc05c2000 - 0xc0628bd8 ( 411 kB)
[ 0.000000] .bss : 0xc0628bfc - 0xc06559e4 ( 180 kB)
[ 0.000000] NR_IRQS:396
[ 0.000000] IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts
[ 0.000000] Total of 128 interrupts on 1 active controller
[ 0.000000] OMAP clockevent source: GPTIMER2 at
[ 0.000000] omap_dm_timer_switch_src: Switching to HW default clocksource(sys_clkin_ck) for timer1, this may impact timekeeping in low power state
[ 0.000000] OMAP clocksource: GPTIMER1 at
[ 0.000000] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
[ 0.000000] Console: colour dummy device 80x30
[ 0.000187] Calibrating delay loop... 718.02 BogoMIPS (lpj=3590144)
[ 0.057164] pid_max: default: 32768 minimum: 301
[ 0.057288] Security Framework initialized
[ 0.057379] Mount-cache hash table entries: 512
[ 0.057739] CPU: Testing write buffer coherency: ok
[ 0.077568] omap_hwmod: gfx: failed to hardreset
[ 0.093857] omap_hwmod: pruss: failed to hardreset
[ 0.094921] print_constraints: dummy:
[ 0.095269] NET: Registered protocol family 16
[ 0.097376] OMAP GPIO hardware version 0.1
[ 0.099966] omap_mux_init: Add partition: #1: core, flags: 0
[ 0.101913] omap_i2c.1: alias fck already exists
[ 0.102771] omap2_mcspi.1: alias fck already exists
[ 0.102994] omap2_mcspi.2: alias fck already exists
[ 0.103673] edma.0: alias fck already exists
[ 0.103693] edma.0: alias fck already exists
[ 0.103711] edma.0: alias fck already exists
[ 0.130534] bio: create slab &bio-0& at 0
[ 0.132679] SCSI subsystem initialized
[ 0.134269] usbcore: registered new interface driver usbfs
[ 0.134584] usbcore: registered new interface driver hub
[ 0.134781] usbcore: registered new device driver usb
[ 0.134921] musb-ti81xx musb-ti81xx: musb0, board_mode=0x13, plat_mode=0x3
[ 0.135188] musb-ti81xx musb-ti81xx: musb1, board_mode=0x13, plat_mode=0x1
[ 0.147230] omap_i2c omap_i2c.1: bus 1 rev2.4.0 at 100 kHz
[ 0.149087] tpsd: JTAGREVNUM 0x0
[ 0.151462] print_constraints: VRTC:
[ 0.152902] print_constraints: VIO: at 1500 mV
[ 0.155207] print_constraints: VDD1: 600 &--& 1500 mV at 1262 mV normal
[ 0.157494] print_constraints: VDD2: 600 &--& 1500 mV at 1137 mV normal
[ 0.158512] print_constraints: VDD3: 5000 mV
[ 0.159914] print_constraints: VDIG1: at 1800 mV
[ 0.161348] print_constraints: VDIG2: at 1800 mV
[ 0.162759] print_constraints: VPLL: at 1800 mV
[ 0.164176] print_constraints: VDAC: at 1800 mV
[ 0.165597] print_constraints: VAUX1: at 1800 mV
[ 0.167021] print_constraints: VAUX2: at 3300 mV
[ 0.168461] print_constraints: VAUX33: at 3300 mV
[ 0.169877] print_constraints: VMMC: at 3300 mV
[ 0.170380] tpsd: No interrupt support, no core IRQ
[ 0.171801] Advanced Linux Sound Architecture Driver Version 1.0.24.
[ 0.172930] Switching to clocksource gp timer
[ 0.188568] musb-hdrc: version 6.0, ?dma?, otg (peripheral+host)
[ 0.188732] musb-hdrc musb-hdrc.0: dma type: pio
[ 0.189032] MUSB0 controller's USBSS revision = 4ea20800
[ 0.189582] musb-hdrc musb-hdrc.0: USB OTG mode controller at e083c000 using PIO, IRQ 18
[ 0.189730] musb-hdrc musb-hdrc.1: dma type: pio
[ 0.190026] MUSB1 controller's USBSS revision = 4ea20800
[ 0.190141] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
[ 0.190211] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
[ 0.190345] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 0.190361] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 0.190374] usb usb1: Product: MUSB HDRC host driver
[ 0.190385] usb usb1: Manufacturer: Linux 3.2.0 musb-hcd
[ 0.190395] usb usb1: SerialNumber: musb-hdrc.1
[ 0.191151] hub 1-0:1.0: USB hub found
[ 0.191182] hub 1-0:1.0: 1 port detected
[ 0.191713] musb-hdrc musb-hdrc.1: USB Host mode controller at e083e800 using PIO, IRQ 19
[ 0.192127] NET: Registered protocol family 2
[ 0.192309] IP route cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.192591] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.192889] TCP bind hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.193128] TCP: Hash tables configured (established 16384 bind 16384)
[ 0.193141] TCP reno registered
[ 0.193164] UDP hash table entries: 256 (order: 0, 4096 bytes)
[ 0.193188] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[ 0.193390] NET: Registered protocol family 1
[ 0.193642] RPC: Registered named UNIX socket transport module.
[ 0.193656] RPC: Registered udp transport module.
[ 0.193665] RPC: Registered tcp transport module.
[ 0.193673] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.193905] NetWinder Floating Point Emulator V0.97 (double precision)
[ 0.212256] VFS: Disk quotas dquot_6.5.2
[ 0.212318] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[ 0.212839] msgmni has been set to 1002
[ 0.215916] alg: No test for stdrng (krng)
[ 0.216572] io scheduler noop registered
[ 0.216587] io scheduler deadline registered
[ 0.216658] io scheduler cfq registered (default)
[ 0.217772] Could not set LED4 to fully on
[ 0.219488] omap_uart.0: ttyO0 at MMIO 0x44e09000 (irq = 72) is a OMAP UART0
[ 0.219961] omap_uart.1: ttyO1 at MMIO 0x (irq = 73) is a OMAP UART1
[ 0.873737] console [ttyO1] enabled
[ 0.877937] omap_uart.2: ttyO2 at MMIO 0x (irq = 74) is a OMAP UART2
[ 0.885743] omap_uart.3: ttyO3 at MMIO 0x481a6000 (irq = 44) is a OMAP UART3
[ 0.893531] omap_uart.4: ttyO4 at MMIO 0x481a8000 (irq = 45) is a OMAP UART4
[ 0.901290] omap_uart.5: ttyO5 at MMIO 0x481aa000 (irq = 46) is a OMAP UART5
[ 0.918251] brd: module loaded
[ 0.926295] loop: module loaded
[ 0.929751] i2c-core: driver [tsl2550] using legacy suspend method
[ 0.936231] i2c-core: driver [tsl2550] using legacy resume method
[ 0.942644] at24 1- byte 24c256 EEPROM, writable, 64 bytes/write
[ 1.002972] No daughter card found
[ 1.006555] at24 1- byte 24c256 EEPROM, writable, 64 bytes/write
[ 1.013824] The board is a Chipsee AM335x SOM.
[ 1.018776] omap_hsmmc.0: alias fck already exists
[ 1.024553] da8xx_lcdc.0: alias fck already exists
[ 1.030014] da8xx_lcdc da8xx_lcdc.0: GLCD: Found INNOLUX_TN92 panel
[ 1.046268] Console: switching to colour frame buffer device 100x30
[ 1.059939] davinci-mcasp.0: alias fck already exists
[ 1.066175] omap-gpmc omap-gpmc: GPMC revision 6.0
[ 1.071178] Registering NAND on CS0
[ 1.077588] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 1.084896] omap2-nand driver initializing
到此处内核死了，请问这是什么原因造成的？谢谢
通过打印信息，可以确定程序死在红色字体那一行：
& && & chip-&cmdfunc(mtd, NAND_CMD_RESET, -1,-1);
& && & /* Send the command for reading device ID*/
& && & chip-&cmdfunc(mtd, NAND_CMD_READID,0x00, -1);
& && & /* Read manufacturer and device IDs */
& && & *maf_id = chip-&read_byte(mtd);
& && & dev_id = chip-&read_byte(mtd);
& && & ......
& &&&通过示波器可以量到am335x一直在向nand flash读数据，所以死到这里，还请帮解答 ，谢谢
另外，我用linux-3.1.0（英倍特的版本）,不会报错，能正常运行，并且可以正确读取man_id和dev_id,说明硬件是没有问题。我现在是用的linux-3.2.0（linux-3.2.0-chipsee-evm.tar.gz）的版本
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如果有时间可以去下我公司论坛，这里面有关于arm335X的一些问题解决的案例，说明。希望能帮到您！&&如果需要我帮助可以通过手机或者QQ 联系我 小汪
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问题已经解决，与mux pin有关
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能帮忙详细说说是怎么解决的么？谢谢！
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热门推荐 /3AM3351 Sitara 处理器 | 德州仪器
(正在供货)
Sitara 处理器
&(英文內容)
&(英文內容)
In English
日本語表示
相关终端应用
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced
with image, graphics processing, peripherals and industrial interface options such as
EtherCAT and PROFIBUS. The devices support high-level
operating systems (HLOS). Linux& and
Android& are available free of charge from TI.
The AM335x
microprocessor contain the subsystems shown in Figure 1-1 and a brief description of each follows:
The microprocessor unit (MPU)
subsystem is based on the ARM Cortex-A8 processor and the
PowerVR SGX&
Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming
The PRU-ICSS is separate from the ARM core,
allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS
enables additional peripheral interfaces and real-time protocols such as
EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet
Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with
its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in
implementing fast, real-time responses, specialized data handling operations, custom peripheral
interfaces, and in offloading tasks from the other processor cores of SoC.
Up to 1-GHz Sitara& ARM& Cortex&-A8 32-Bit RISC Processor NEON& SIMD Coprocessor 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity) 256KB of L2 Cache With Error Correcting Code (ECC) 176KB of On-Chip Boot ROM 64KB of Dedicated RAM Emulation and Debug - JTAG Interrupt Controller (up to 128 Interrupt Requests) On-Chip Memory (Shared L3 RAM) 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM Accessible to All Masters Supports Retention for Fast Wakeup External Memory Interfaces (EMIF) mDDR(LPDDR), DDR2, DDR3, DDR3L Controller: mDDR: 200-MHz Clock (400-MHz Data Rate) DDR2: 266-MHz Clock (532-MHz Data Rate) DDR3: 400-MHz Clock (800-MHz Data Rate) DDR3L: 400-MHz Clock (800-MHz Data Rate) 16-Bit Data Bus 1GB of Total Addressable Space Supports One x16 or Two x8 Memory Device Configurations General-Purpose Memory Controller (GPMC) Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM) Uses BCH Code to Support 4-, 8-, or 16-Bit ECC Uses Hamming Code to Support 1-Bit ECC Error Locator Module (ELM) Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) Supports Protocols such as EtherCAT&, PROFIBUS, PROFINET, EtherNet/IP&, and More Two Programmable Real-Time Units (PRUs) 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz 8KB of Instruction RAM With Single-Error Detection (Parity) 8KB of Data RAM With Single-Error Detection (Parity) Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator Enhanced GPIO Module Provides Shift- In/Out Support and Parallel Latch on External Signal
12KB of Shared RAM With Single-Error Detection (Parity) Three 120-Byte Register Banks Accessible by Each PRU Interrupt Controller (INTC) for Handling System Input Events Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS Peripherals Inside the PRU-ICSS: One UART Port With Flow Control Pins, Supports up to 12 Mbps One Enhanced Capture (eCAP) Module Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT One MDIO Port Power, Reset, and Clock Management (PRCM) Module
Controls the Entry and Exit of Stand-By and Deep-Sleep Modes Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing Clocks Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock) Power Two Nonswitchable Power Domains (Real- Time Clock [RTC], Wake-Up Logic [WAKEUP]) Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER]) Implements SmartReflex& Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS]) Dynamic Voltage Frequency Scaling (DVFS) Real-Time Clock (RTC) Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO Independent Power-on-Reset (RTC_PWRONRSTn) Input Dedicated Input Pin (EXT_WAKEUP) for External Wake Events Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification) Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains Peripherals Up to Two USB 2.0 High-Speed OTG Ports With Integrated PHY Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps) Integrated Switch Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces Ethernet MACs and Switch Can Operate Independent of Other Functions IEEE 1588v2 Precision Time Protocol (PTP) Up to Two Controller-Area Network (CAN) Ports Supports CAN Version 2 Parts A and B Up to Two Multichannel Audio Serial Ports (McASPs) Transmit and Receive Clocks up to 50 MHz Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats) FIFO Buffers for Transmit and Receive (256 Bytes) Up to Six UARTs All UARTs Support IrDA and CIR Modes All UARTs Support RTS and CTS Flow Control UART1 Supports Full Modem Control Up to Two Master and Slave McSPI Serial Interfaces Up to Two Chip Selects Up to 48 MHz Up to Three MMC, SD, SDIO Ports 1-, 4- and 8-Bit MMC, SD, SDIO Modes MMCSD0 has Dedicated Power Rail for 1.8-V or 3.3-V Operation Up to 48-MHz Data Transfer Rate Supports Card Detect and Write Protect Complies With MMC4.3, SD, SDIO 2.0 Specifications Up to Three I2C Master and Slave Interfaces Standard Mode (up to 100&kHz) Fast Mode (up to 400 kHz) Up to Four Banks of General-Purpose I/O (GPIO) Pins 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins) GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank) Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs Eight 32-Bit General-Purpose Timers DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks DMTIMER4–DMTIMER7 are Pinned Out One Watchdog Timer SGX530 3D Graphics Engine Tile-Based Architecture Delivering up to 20 Million Polygons per Second Universal Scalable Shader Engine (USSE) is
a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0 Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0, and OpenMax Fine-Grained Task Switching, Load Balancing, and Power Management Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction Programmable High-Quality Image Anti- Aliasing Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture LCD Controller Up to 24-Bit Data O 8 Bits per Pixel (RGB) Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock) Integrated LCD Interface Display Driver (LIDD) Controller Integrated Raster Controller Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer 512-Word Deep Internal FIFO Supported Display Types: Character Displays - Uses LIDD Controller to Program these Displays Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel 12-Bit Successive Approximation Register (SAR) ADC 200K Samples per Second Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface Up to Three 32-Bit eCAP Modules Configurable as Three Capture Inputs or Three Auxiliary PWM utputs Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs) Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls Configurable as Six Single-Ended, Six Dual- Edge Symmetric, or Three Dual-Edge Asymmetric Outputs Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules Device Identification Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable Production ID Device Part Number (Unique JTAG ID) Device Revision (Readable by Host ARM) Debug Interface Support JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug Supports Device Boundary Scan Supports IEEE 1500 DMA On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for: Transfers to and from On-Chip Memories Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals) Inter-Processor Communication (IPC) Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS Mailbox Registers that Generate Interrupts Four Initiators (Cortex-A8, PRCM, PRU0, PRU1) Spinlock has 128 Software-Assigned Lock Registers Security Crypto Hardware Accelerators (AES, SHA, RNG) Secure Boot Boot Modes Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin Packages: 298-Pin S-PBGA-N298 Via Channel Package (ZCE Suffix), 0.65-mm Ball Pitch 324-Pin S-PBGA-N324 Package (ZCZ Suffix), 0.80-mm Ball Pitch
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特色工具和软件
(模拟模型)
(评估模块和开发板)
(评估模块和开发板)
ARM MHz (Max.)
Display Outputs
Graphics Acceleration
Co-Processor(s)
Industrial Protocols
Serial I/O
Operating Temperature Range
Operating Systems
Applications
Other On-Chip Memory
On-Chip L2 Cache
1 ARM Cortex-A8&
1 ARM Cortex-A8&
1 ARM Cortex-A8&
1 ARM Cortex-A8&
1 ARM Cortex-A8&
1 ARM Cortex-A8&
1 ARM Cortex-A8&
300 600 800 1000&
600 800 1000&
300 600 800&
300 600 800&
600 800 1000&
600 1200 1600 2000&
1200 1600 2000&
600 1200 1600&
600 1200 1600&
1200 1600 2000&
LPDDR DDR2 DDR3 DDR3L&
LPDDR DDR2 DDR3 DDR3L&
LPDDR DDR2 DDR3 DDR3L&
LPDDR DDR2 DDR3 DDR3L&
LPDDR DDR2 DDR3 DDR3L&
LPDDR DDR2 DDR3 DDR3L&
LPDDR DDR2 DDR3 DDR3L&
10/100/1000&
2-Port 1Gb Switch&
2-Port 1Gb Switch&
2-Port 1Gb Switch&
2-Port 1Gb Switch&
2-Port 1Gb Switch&
2-Port 1Gb Switch&
2 PRU-ICSS&
2 PRU-ICSS&
2 PRU-ICSS&
2 PRU-ICSS&
1588 EtherNet/IP PROFIBUS PROFINET RT/IRT SERCOS III&
1588 EtherCAT EtherNet/IP Ethernet POWERLINK PROFIBUS PROFINET RT/IRT SERCOS III&
1588 EtherNet/IP PROFIBUS PROFINET RT/IRT SERCOS III&
1588 EtherCAT EtherNet/IP Ethernet POWERLINK PROFIBUS PROFINET RT/IRT SERCOS III&
I2C SPI UART USB&
CAN I2C SPI UART USB&
CAN I2C SPI UART USB&
CAN I2C SPI UART USB&
CAN I2C SPI UART USB&
CAN I2C SPI UART USB&
CAN I2C SPI UART USB&
-40 to 105 0 to 90&
-40 to 105 -40 to 125 -40 to 90 0 to 90&
-40 to 105 -40 to 90 0 to 90&
-40 to 105 -40 to 90 0 to 90&
-40 to 105 -40 to 90&
-40 to 105 0 to 90&
-40 to 105&
Linux Android Windows Embedded CE&
Linux Android Windows Embedded CE&
Neutrino Integrity Windows Embedded CE Linux VxWorks Android&
Neutrino Integrity Windows Embedded CE Linux VxWorks Android&
Neutrino Integrity Windows Embedded CE Linux VxWorks Android&
Neutrino Integrity Windows Embedded CE Linux VxWorks Android&
Neutrino Integrity Windows Embedded CE Linux VxWorks Android&
Automotive Industrial Personal Electronics&
Automotive Industrial Personal Electronics&
Automotive Industrial Personal Electronics&
Automotive Industrial Personal Electronics&
Automotive Industrial Personal Electronics&
Automotive Industrial Personal Electronics&
Automotive Industrial Personal Electronics&
256 KB (ARM Cortex-A8)&
256 KB (ARM Cortex-A8)&
256 KB (ARM Cortex-A8)&
256 KB (ARM Cortex-A8)&
256 KB (ARM Cortex-A8)&
256 KB (ARM Cortex-A8)&
256 KB (ARM Cortex-A8)&}