LPC1788 SDRAM运行程序 - ou_ou - 博客园
折腾了很久 终于解决了 从SDRAM中运行APP程序。说明：LPC1788 本身有512K的flash和96K的RAM。支持TFT和SDRAM 这算是跟别家cortex-M3架构MCU相比较的一个亮点。我这个项目需要使用GUI，NXP有免费的emwin库，这也是一个极大的便利。我这个项目显示图形比较多，没有配置SD卡或NorFlash，硬件的大致结构式 LPC1788+NandFlash(4M)+SDRAM(16M)+4.3寸TFT。运行过程中显示的图片比较多，客户方不想把图形以及字库文件存在NandFlash中，只有通过转换成C的方式编译在一起，Oh my god! 固件超大，远远超过512K。我一开始以为 LPC1788 应该会跟STM32F103ZE这个片子一样很容易就可以实现SDRAM中运行，没想到根本不行。NXP的官方资料也比较少，求人不如求己，还是自己琢磨吧。LPC1788 支持MPU，所以一开始我的程序装载到SDRAM中无法运行 也是因为MPU的缘故。知道了原因就近似等于找到了解决办法。google了很久终于琢磨出来了，需要在MPU中配置SDRAM，才可以运行程序的。我把其中的代码贴上来吧，有兴趣的可以看看。#include "core_cm3.h"#include &stdint.h&#include &string.h&//运行指定地址的程序void JUMP_TO_APP(unsigned long&&address){& & __ASM("LDR SP, [R0]& &&&;Load new stack pointer address");& & __ASM("LDR PC, [R0, #4] ;Load new program counter address");}//从指定了NandFlash地址 复制数据到SDRAM 并运行SDRAM程序void board_jump_to_app(void){& & //关闭全部中断& & NVIC_DeInit();& & //Copy target firmware to SDRAM& & memcpy((void *)SDRAM_BASE_ADDR,(void *)NOR_FLASH_BASE,NOR_FLASH_SIZE);& & __set_MSP(SDRAM_BASE_ADDR);& & JUMP_TO_APP(SDRAM_BASE_ADDR);}//判断 NandFlash中程序的有效性。LPC1788 会在0x1C偏移处设置校验码，//return 1-& OK ,others is erroruint8_t app_checksum_is_correct(void){& && & uint32_t cksum, *& & buff = (uint32_t *)NOR_FLASH_BASE;//判断App程序的第一个跳转指令地址 是否是SDRAM的高位地址&&& & if((buff[1] & SDRAM_BASE_ADDR) != SDRAM_BASE_ADDR)& && &&&return 0;& &//以下是校验码算法，各位自己琢磨& & cksum = 0;& & for (i = 0; i & 7; ++i) {& && &&&cksum += buff[i];& & }& & cksum = (0xFFFFFFFF - cksum + 1);//判断校验码是否符合要求，返回1 表示OK& & return ((cksum == buff[7]) && (buff[7] != 0));}/**********************************************************************//*& && && && && && && && && &MPU 设置& && && && && && && && && && && && && && && && && && && && && && && && && && &*//**********************************************************************//* Region size definitions */#define MPU_REGION_SIZE_32B& &&&0x04#define MPU_REGION_SIZE_64B& &&&0x05#define MPU_REGION_SIZE_128B& & 0x06#define MPU_REGION_SIZE_256B& & 0x07#define MPU_REGION_SIZE_512B& & 0x08#define MPU_REGION_SIZE_1KB& &&&0x09#define MPU_REGION_SIZE_2KB& &&&0x0A#define MPU_REGION_SIZE_4KB& &&&0x0B#define MPU_REGION_SIZE_8KB& &&&0x0C#define MPU_REGION_SIZE_16KB& & 0x0D#define MPU_REGION_SIZE_32KB& & 0x0E#define MPU_REGION_SIZE_64KB& & 0x0F#define MPU_REGION_SIZE_128KB& &0x10#define MPU_REGION_SIZE_256KB& &0x11#define MPU_REGION_SIZE_512KB& &0x12#define MPU_REGION_SIZE_1MB& &&&0x13#define MPU_REGION_SIZE_2MB& &&&0x14#define MPU_REGION_SIZE_4MB& &&&0x15#define MPU_REGION_SIZE_8MB& &&&0x16#define MPU_REGION_SIZE_16MB& & 0x17#define MPU_REGION_SIZE_32MB& & 0x18#define MPU_REGION_SIZE_64MB& & 0x19#define MPU_REGION_SIZE_128MB& &0x1A#define MPU_REGION_SIZE_256MB& &0x1B#define MPU_REGION_SIZE_512MB& &0x1C#define MPU_REGION_SIZE_1GB& &&&0x1D#define MPU_REGION_SIZE_2GB& &&&0x1E#define MPU_REGION_SIZE_4GB& &&&0x1F/* Access permission definitions */#define MPU_NO_ACCESS& && && && && && && && && &0x00#define MPU_PRIVILEGED_ACESS_USER_NO_ACCESS& &&&0x01#define MPU_PRIVILEGED_RW_USER_READ_ONLY& && &&&0x02#define MPU_FULL_ACCESS& && && && && && && && & 0x03#define MPU_UNPREDICTABLE& && && && && && && &&&0x04#define MPU_PRIVILEGED_READ_ONLY_USER_NO_ACCESS 0x05#define MPU_READ_ONLY& && && && && && && && && &0x06/* RASR bit definitions */#define MPU_RASR_REGION_SIZE(n)& && && &((uint32_t)(n&&1))#define MPU_RASR_ACCESS_PERMISSION(n)& &((uint32_t)(n&&24))#define MPU_REGION_ENABLE& && && && && &((uint32_t)(1&&0))void board_mpu_init(void){& & /* - Region 0: 0x - 0x0007FFFF --- on-chip non-volatile memory& &&&*& && &+ Size: 512kB& &&&*& && &+ Acess permission: full access& &&&*/& & MPU-&RNR&&= 0;//indicate MPU region 0& & MPU-&RBAR = 0x; // update the base address for the region 0& & MPU-&RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)& &&&//full access& && && && && & |MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_512KB)& & //512Kb size& && && && && & |MPU_REGION_ENABLE;& && && && && && && && && &&&//region enable& & /* - Region 1: 0x - 0x1000FFFF --- on-chip SRAM& &&&*& && &+ Size: 64kB& &&&*& && &+ Access permission: full access& &&&*/& & MPU-&RNR = 1;& & MPU-&RBAR = 0x; // update the base address for the region 1& & MPU-&RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)& && && && && & |MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_64KB)& && && && && & |MPU_REGION_ENABLE;& &&&/* - Region 2: 0x - 0x400FFFFF --- APB peripheral& &&&*& && &+ Size: 1MB& &&&*& && &+ Access permission: full access& &&&*/& & MPU-&RNR = 2;& & MPU-&RBAR = 0x; // update the base address for the region 2& & MPU-&RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)& && && && && & |MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_1MB)& && && && && & |MPU_REGION_ENABLE;& &&&/* - Region 3: 0x - 0x200BFFFF --- AHB peripheral& &&&*& && &+ Size: 256KB& &&&*& && &+ AP=b011: full access& &&&*/& & MPU-&RNR = 3;& & MPU-&RBAR = 0x; // update the base address for the region 3& & MPU-&RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)& && && && && & |MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_256KB)& && && && && & |MPU_REGION_ENABLE;& &&&/* - Region 4: 0xE0000000 - 0xE00FFFFF --- System control& &&&*& && &+ Size: 1MB& &&&*& && &+ Access permission: full access& &&&*/& & MPU-&RNR = 4;& & MPU-&RBAR = 0xE0000000; // update the base address for the region 4& & MPU-&RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)& && && && && & |MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_1MB)& && && && && & |MPU_REGION_ENABLE;& &&&/* - Region 5:0x - 0x20007FFF --- on chip SRAM& &&&*& && &+ Size: 32kB& &&&*& && &+ Access permission: full access& &&&*/& & MPU-&RNR = 5;& & MPU-&RBAR = 0x; // update the base address for the region 5& & MPU-&RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)& && && && && & |MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_32KB)& && && && && & |MPU_REGION_ENABLE;& & /* - Region 6:0xA0000000 - 0xA1000000 --- NorFlash& & *& && &+ Size: 16MB& & *& && &+ Access permission: full access& & */& &MPU-&RNR = 6;& &MPU-&RBAR = 0x; // update the base address for the region 5& &MPU-&RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)& && && && && &|MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_16MB)& && && && && &|MPU_REGION_ENABLE;& & /* - Region 6:0xA0000000 - 0xA1000000 --- Ext SRAM& & *& && &+ Size: 16MB& & *& && &+ Access permission: full access& & */& &MPU-&RNR = 7;& &MPU-&RBAR = 0xA0000000; // update the base address for the region 5& &MPU-&RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)& && && && && &|MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_16MB)& && && && && &|MPU_REGION_ENABLE;& &SCB-&SHCSR |=(1&&16);& &//Enable Memory management fault& &MPU-&CTRL =(1&&0);& && &//Enable the MPU////& & _DBG_("Setup MPU: \n\r"////& && && & "This provide 6 regions: \n\r"////& && && & "Region 0 - Privileged code: 0x - 0x0007FFFF(512kB)\n\r"////& && && & "Region 1 - Privileged data: 0x - 0x1000FFFF(64kB)\n\r"////& && && & "Region 2 - APB Peripheral:&&0x - 0x400FFFFF(1MB)\n\r"////& && && & "Region 3 - AHB peripheral:&&0x - 0x200BFFFF(256KB)\n\r"////& && && & "Region 4 - System control:&&0xE0000000 - 0xE00FFFFF(1MB)\n\r"////& && && & "Region 5 - On-chip SRAM:& & 0x - 0x20007FFF(32kB)\n\r"////& && && & "Region 6 - Ext SRAM& && && &0xA0000000 - 0xAMB)\n\r");//}通过 执行board_mpu_init() 函数以后，NandFlash 和 SDRAM中都可以直接运行程序。但是NandFlash中运行简直是太慢了，我受不了。
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Nand Flash Interface using External Memory Controller LPC1788
Nand Flash Interface using External Memory Controller LPC1788 Structure of the Nand Flash MemoryMemory IC: 1Page 1Block 1Memory IC K9F1G08U0C = = = 1Gbit Nand Flash 2KB + 64Bytes for EC
C* 64Pages 1024 Blocks*ECC bytes are extra in each page. These bytes are not used for data storage.The IC does not have separate Address and Data lines as in traditional memories. It has 8IO lines to transfer the Address or Data or Command. Depending on the command sent, the operations are performed. The commands are listed in the datasheet of the memory IC. The address is sent on the IO lines and ALE is generated to latch the address into the IC. The address is generally of 4bytes. Similarly the command is sent on IO lines and CLE is generated to latch the command. The command can be of 1/2 bytes. The data is written page wise and read page wise. But the data erase is always Block wise. In other words, a single page cannot be erased, but data can be read or written from a page. Read/!Busy signal is used to check the status of the Nand Flash. While Nand flash is busy in doing some internal operations, R/!B = 0. If R/!B = 1, then the Nand flash is ready. Also, while Nand flash is busy in performing internal operations, the logic level on CS signal has no effect i.e. even if the CS is not asserted, the internal operations continue. OE C Read signal, WE C Write signalEMC descriptionNand flash and Nor flash are static type memories. From the user manual, Memory Range 0x C 0x83FF FFFF 0x C 0x93FF FFFF 0x C 0x9BFF FFFF 0x9C00 0000 C 0x9FFF FFFF D0 C D7 Data lines. Disable the Address Mirror.Chip select CS0 CS1 CS2 CS3Connections LPC1788 Pins D0 - D7 A24 A25 GPIO P2.21 CS1Nand Flash Driver IO0 C IO7 ALE CLE R/!B CEDescription for connections A24 is connected to the ALE. Therefore, address can be latched into the Nand flash by writing the data to the memory location, calculated in the following manner:CS1 is used. Hence, the Base address becomes 0x + (0x * 1) = 0x ALE Address = 0x CLE Address = 0x Therefore, the actual addresses are ALE Address = 0x CLE Address = 0xCorrect according to user manual of LPC1788--& As ‘A24’ address line is used, hence the 24th bit is high. --& As ‘A25’ address line is used, hence the 24th bit is high.In some development boards, A19 and A20 are connected. Accordingly, 0x & 0x are the addresses used.
Cortex-M3 (NXP LPC1788)之外部中断操作分类: Cortex-M3(NXP LPC1788) 16:12 1182 人阅读 评论(0) 收藏 举报 工作 c 要使用 LPC1788 的外部...LPC1788 共有 5 个串口 Uart0~Uart4,跟具开发板的资源,将使用 Uart2 进行简单的串口输出和 输入中断的操作。开发板上使用 74HC4052 多路开关对 UART2 的 ... LPC1788-LPC1768调试问题解决-ULINK2_电子/电路_工程科技_专业资料。问题都是:弹出对话框:Flash Downloaded failed - target DLL has been cancelled。调试输出:... 基于LPC2214简单的nandflash读写_电子/电路_工程科技_专业资料。本程序是基于LPC2214对nandflash的简单读写,没有ECC校验,只是简单的读和写,方便学习之用。经本人...Embest NXP LPC178832位ARM Cortex-M3 MCU开发方案...MII/RMII interface and associated DMA controller. ...flash96KB SRAM External Memory:128MB NAND FLASH... pin functions for SDRAM, NOR and NAND flash interfacing EMC_PINSEL5_Val ... MAM_SETUP LPC2478 启动代码分析 2 ; Setup External Memory Controller ---...Flash 地址: NAND Flash: 0x NXP LPC2478 使用手册 2008 LPC2478 内存映像 1.3 开发板包括套件: 开发板包括套件:一块已经测好的 LPC2478 开发板...?? ; External Interrupts DCD WDT_IRQHandler DCD...__use_two_region_memory EXPORT __user_initial_...LPC1788有内部 Flash, 所以上点从内部 Flash 启动,... Cortex-M0(NXP LPC11C14)启动代码分析_计算机软件... IP2111 Flash Memory Controller ; PIO INT3 ; ...__use_two_region_memory EXPORT __user_initial_...? Supports external wait signals to expand the ...Supports booting from NAND flash memory. ? 4KB ...LPC3600 Timing controller embedded for LTS350Q1-...
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