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win7 64位下安装 quartus 11.1 or 12.1 无法用modelsim产生Nios核仿真文件？
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win7 64位下安装 quartus 11.1 or 12.1 无法用modelsim产生Nios核仿真文件？
quartus 11.1 sp2 64位
modelsim 10.0c
quartus 12.1 sp1 64位
modelsim-ae 10.1b
quartus 11.1 sp2 32位
modelsim 10.0c
quartus 12.1 sp1 32位
modelsim-ae 10.1b
quartus 11.1 sp1 32位
modelsim-ae 10.0c
按照黑金&&NIOSII那些事儿-Qsys_EP4CE15&&第一章 hello world 生成的 nios 核 运行没问题
现在在Qsys生成软核，加上仿真输出
Create testbench Qsys system: Standard,BFMs for standard Avlon interfaces
Create testbench simulation model:Verilog
环境1,2,3,4出错
Error: nios2: can't read &plainTEXTfound&: no such variable
& & while executing
&return $plainTEXTfound&
& & (procedure &sub_generate_create_processor_rtl& line 112)
& & invoked from within
&sub_generate_create_processor_rtl& && && &&&&$output_name& &$output_directory& &$rtl_ext& &$simgen&&
& & invoked from within
&set plainTEXTfound [sub_generate_create_processor_rtl& && && &&&&$output_name& &$output_directory& &$rtl_ext& &$simgen&]&
& & (procedure &generate& line 3)
& & invoked from within
&generate& && && && && & &$NAME& &$output_directory& &$rtl_ext& &$simgen&&
& & invoked from within
&set plainTEXTfound [generate& && && && && & &$NAME& &$output_directory& &$rtl_ext& &$simgen&]&
& & (procedure &generate_with_plaintext& line 5)
& & invoked from within
&generate_with_plaintext &$NAME& &$rtl_ext& &$simgen&&
& & (procedure &sub_sim_verilog& line 5)
& & invoked from within
&sub_sim_verilog TestHJ_CPU_nios2&
环境5没问题！
有什么办法解决吗？是哪里破解不对吗？
难道只能用回WIN7 32位？
ModelSim-Altera Edition software
ModelSim-Altera Starter Edition software
32 bit support only
与这有关吗？
但是其它不用到IP核的仿真都很好，
用到IP核时，就生成不了带仿真的软核？
而在WIN7 32位系统中，用到IP核，也可以生成带仿真的软核。
& & 我曾经在WIN7 64位旗舰SP1，Q2的64位12.1SP1用modelsim SE 10.1C 64位进行过LED的仿真测试，正常通过。
回复&&zglak
& & 我曾经在WIN7 64位旗舰SP1，Q2的64位12.1SP1用modelsim SE 10.1C 64位进行过LED的仿 ...
rabbitpan0317 发表于
& & 谢谢你！我试下。
modelsim SE 是不是不需要注册啊？
回复&&zglak
& & 我曾经在WIN7 64位旗舰SP1，Q2的64位12.1SP1用modelsim SE 10.1C 64位进行过LED的仿 ...
rabbitpan0317 发表于
& & 我刚刚下载了ASE，安装了一试，还是一样不行啊？奇怪了……
回复&&zglak
& & 我曾经在WIN7 64位旗舰SP1，Q2的64位12.1SP1用modelsim SE 10.1C 64位进行过LED的仿 ...
rabbitpan0317 发表于
& & 又安装了SE还是一样……看样子是不是我的系统有问题，我再试试。
& & 最近的事有些忙不过来了。还不行留个QQ吧，我争取周末联系你。
回复&&zglak
& & 最近的事有些忙不过来了。还不行留个QQ吧，我争取周末联系你。
rabbitpan0317 发表于
& & 谢谢你！我又重装安装了纯净Win7x64系统，还是不行……
周未晚上好不？远程控制看看：）
& &&&qq联系不上，你的报错信息不完全，感觉上是你的和谐没有和谐好造成的。64位和谐要将32位和64位都和谐一遍才OK。因为altera 64位软件只是在32位上做了个大补丁，很多东东还和32位的有关联。
回复&&zglak
& &&&qq联系不上，你的报错信息不完全，感觉上是你的和谐没有和谐好造成的。64位和谐要将 ...
rabbitpan0317 发表于
& & 不好意思，昨晚公司加班去了。我把32，64都和谐了啊，还是不行。那什么时候有时间提前留个言好不？帮我远程控制看看：）
& &再补上我的报错信息。
Info: nios2: Info: Command: quartus_map kernel_nios2 --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_arbitrary_blackbox=+kernel_nios2_test_+kernel_nios2_mult_+kernel_nios2_jtag_debug_module_+kernel_nios2_oci_test_+kernel_nios2_jtag_debug_module_+kernel_nios2_jtag_debug_module_tck --simgen_parameter=CBX_HDL_LANGUAGE=verilog,SIMGEN_RAND_POWERUP_FFS=OFF,simgen_initialization_file=simgen_init.txt
Info: nios2: Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_test_bench.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_test_bench
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_mult_cell.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_mult_cell
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_wrapper.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_wrapper
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_oci_test_bench.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_oci_test_bench
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_sysclk.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_sysclk
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_tck.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_tck
Info: nios2: Warning (292000): FLEXlm software error: Invalid (inconsistent) license key.&&The license key and data for the feature do not match.&&This usually happens when a license file has been altered. Feature:& && & 6AF7_00A2 License path:&&G:\License\Altera_license_121_64. FLEXnet Licensing error:-8,523 For further information, refer to the FLEXnet Licensing documentation, available at &&.
Info: nios2: Warning (292000): FLEXlm software error: Invalid (inconsistent) license key.&&The license key and data for the feature do not match.&&This usually happens when a license file has been altered. Feature:& && & 6AF7_00A2 License path:&&G:\License\Altera_license_121_64. FLEXnet Licensing error:-8,523 For further information, refer to the FLEXnet Licensing documentation, available at &&.
Info: nios2: Error (10003): Can't open encrypted VHDL or Verilog HDL file &C:/Users/ZGL/AppData/Local/Temp/alt.dir/0023_nios2_gen/simgen_tmp_0/kernel_nios2.v& -- current license file does not contain a valid license for encrypted file
Info: nios2: Info (12021): Found 0 design units, including 0 entities, in source file kernel_nios2.v
Info: nios2: Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 2 warnings
Info: nios2:& &&&Error: Peak virtual memory: 335 megabytes
Info: nios2:& &&&Error: Processing ended: Mon Mar 25 22:36:45 2013
Info: nios2:& &&&Error: Elapsed time: 00:00:02
Info: nios2:& &&&Error: Total CPU time (on all processors): 00:00:02
Info: nios2: #
22:36:46 (*)& &&C:/altera/12.1sp1/quartus/bin/quartus_map& kernel_nios2 --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_arbitrary_blackbox=&+kernel_nios2_test_+kernel_nios2_mult_+kernel_nios2_jtag_debug_module_+kernel_nios2_oci_test_+kernel_nios2_jtag_debug_module_+kernel_nios2_jtag_debug_module_tck& --simgen_parameter=CBX_HDL_LANGUAGE=verilog,SIMGEN_RAND_POWERUP_FFS=OFF,simgen_initialization_file=simgen_init.txt command returned 3
Info: nios2: child process exited abnormally
Error: nios2: Failed to generate module kernel_nios2
Info: nios2: Done RTL generation for module 'kernel_nios2'
Error: nios2: can't read &plainTEXTfound&: no such variable
& & while executing
&return $plainTEXTfound&
& & (procedure &sub_generate_create_processor_rtl& line 112)
& & invoked from within
&sub_generate_create_processor_rtl& && && &&&&$output_name& &$output_directory& &$rtl_ext& &$simgen&&
& & invoked from within
&set plainTEXTfound [sub_generate_create_processor_rtl& && && &&&&$output_name& &$output_directory& &$rtl_ext& &$simgen&]&
& & (procedure &generate& line 3)
& & invoked from within
&generate& && && && && & &$NAME& &$output_directory& &$rtl_ext& &$simgen&&
& & invoked from within
&set plainTEXTfound [generate& && && && && & &$NAME& &$output_directory& &$rtl_ext& &$simgen&]&
& & (procedure &generate_with_plaintext& line 5)
& & invoked from within
&generate_with_plaintext &$NAME& &$rtl_ext& &$simgen&&
& & (procedure &sub_sim_verilog& line 5)
& & invoked from within
&sub_sim_verilog kernel_nios2&
Info: nios2: &kernel_inst& instantiated altera_nios2_qsys &nios2&
Error: Generation stopped, 39 or more modules remaining
Info: kernel_tb: Done kernel_tb& with 27 modules, 5 files, 218330 bytes
Error: ip-generate failed with exit code 1: 3 Errors, 0 Warnings
Error: There were errors creating the testbench system.
Info: Finished: Create testbench Qsys system
Info: nios2: Info: Command: quartus_map kernel_nios2 --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_arbitrary_blackbox=+kernel_nios2_test_+kernel_nios2_mult_+kernel_nios2_jtag_debug_module_+kernel_nios2_oci_test_+kernel_nios2_jtag_debug_module_+kernel_nios2_jtag_debug_module_tck --simgen_parameter=CBX_HDL_LANGUAGE=verilog,SIMGEN_RAND_POWERUP_FFS=OFF,simgen_initialization_file=simgen_init.txt
Info: nios2: Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_test_bench.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_test_bench
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_mult_cell.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_mult_cell
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_wrapper.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_wrapper
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_oci_test_bench.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_oci_test_bench
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_sysclk.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_sysclk
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_tck.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_tck
Info: nios2: Warning (292000): FLEXlm software error: Invalid (inconsistent) license key.&&The license key and data for the feature do not match.&&This usually happens when a license file has been altered. Feature:& && & 6AF7_00A2 License path:&&G:\License\Altera_license_121_64. FLEXnet Licensing error:-8,523 For further information, refer to the FLEXnet Licensing documentation, available at &&.
Info: nios2: Warning (292000): FLEXlm software error: Invalid (inconsistent) license key.&&The license key and data for the feature do not match.&&This usually happens when a license file has been altered. Feature:& && & 6AF7_00A2 License path:&&G:\License\Altera_license_121_64. FLEXnet Licensing error:-8,523 For further information, refer to the FLEXnet Licensing documentation, available at &&.
Info: nios2: Error (10003): Can't open encrypted VHDL or Verilog HDL file &C:/Users/ZGL/AppData/Local/Temp/alt.dir/0023_nios2_gen/simgen_tmp_0/kernel_nios2.v& -- current license file does not contain a valid license for encrypted file
Info: nios2: Info (12021): Found 0 design units, including 0 entities, in source file kernel_nios2.v
Info: nios2: Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 2 warnings
Info: nios2:& &&&Error: Peak virtual memory: 335 megabytes
Info: nios2:& &&&Error: Processing ended: Mon Mar 25 22:36:45 2013
Info: nios2:& &&&Error: Elapsed time: 00:00:02
Info: nios2:& &&&Error: Total CPU time (on all processors): 00:00:02
Info: nios2: #
22:36:46 (*)& &&C:/altera/12.1sp1/quartus/bin/quartus_map& kernel_nios2 --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_arbitrary_blackbox=&+kernel_nios2_test_+kernel_nios2_mult_+kernel_nios2_jtag_debug_module_+kernel_nios2_oci_test_+kernel_nios2_jtag_debug_module_+kernel_nios2_jtag_debug_module_tck& --simgen_parameter=CBX_HDL_LANGUAGE=verilog,SIMGEN_RAND_POWERUP_FFS=OFF,simgen_initialization_file=simgen_init.txt command returned 3
Info: nios2: child process exited abnormally
Error: nios2: Failed to generate module kernel_nios2
Info: nios2: Done RTL generation for module 'kernel_nios2'
Error: nios2: can't read &plainTEXTfound&: no such variable
& & while executing
&return $plainTEXTfound&
& & (procedure &sub_generate_create_processor_rtl& line 112)
& & invoked from within
&sub_generate_create_processor_rtl& && && &&&&$output_name& &$output_directory& &$rtl_ext& &$simgen&&
& & invoked from within
&set plainTEXTfound [sub_generate_create_processor_rtl& && && &&&&$output_name& &$output_directory& &$rtl_ext& &$simgen&]&
& & (procedure &generate& line 3)
& & invoked from within
&generate& && && && && & &$NAME& &$output_directory& &$rtl_ext& &$simgen&&
& & invoked from within
&set plainTEXTfound [generate& && && && && & &$NAME& &$output_directory& &$rtl_ext& &$simgen&]&
& & (procedure &generate_with_plaintext& line 5)
& & invoked from within
&generate_with_plaintext &$NAME& &$rtl_ext& &$simgen&&
& & (procedure &sub_sim_verilog& line 5)
& & invoked from within
&sub_sim_verilog kernel_nios2&
Info: nios2: &kernel_inst& instantiated altera_nios2_qsys &nios2&
Error: Generation stopped, 39 or more modules remaining
Info: kernel_tb: Done kernel_tb& with 27 modules, 5 files, 218330 bytes
Error: ip-generate failed with exit code 1: 3 Errors, 0 Warnings
Error: There were errors creating the testbench system.
Info: Finished: Create testbench Qsys system
Kyle&&22:53:34
Info: nios2: Info: Command: quartus_map kernel_nios2 --simgen --ini=disable_check_quartus_compatibility_qsys_only=on --simgen_arbitrary_blackbox=+kernel_nios2_test_+kernel_nios2_mult_+kernel_nios2_jtag_debug_module_+kernel_nios2_oci_test_+kernel_nios2_jtag_debug_module_+kernel_nios2_jtag_debug_module_tck --simgen_parameter=CBX_HDL_LANGUAGE=verilog,SIMGEN_RAND_POWERUP_FFS=OFF,simgen_initialization_file=simgen_init.txt
Info: nios2: Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_test_bench.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_test_bench
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_mult_cell.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_mult_cell
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_wrapper.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_wrapper
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_oci_test_bench.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_oci_test_bench
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_sysclk.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_sysclk
Info: nios2: Info (12021): Found 1 design units, including 1 entities, in source file kernel_nios2_jtag_debug_module_tck.v
Info: nios2:& &&&Info (12023): Found entity 1: kernel_nios2_jtag_debug_module_tck
Info: nios2: Warning (292000): FLEXlm software error: Invalid (inconsistent) license key.&&The license key and data for the feature do not match.&&This usually happens when a license file has been altered. Feature:& && & 6AF7_00A2 License path:&&G:\License\Altera_license_121_64. FLEXnet Licensing error:-8,523 For further information, refer to the FLEXnet Licensing documentation, available at &&.
Info: nios2: Warning (292000): FLEXlm software error: Invalid (inconsistent) license key.&&The license key and data for the feature do not match.&&This usually happens when a license file has been altered. Feature:& && & 6AF7_00A2 License path:&&G:\License\Altera_license_121_64. FLEXnet Licensing error:-8,523 For further information, refer to the FLEXnet Licensing documentation, available at &&.
本帖最后由 zglak 于
20:13 编辑
回复&&zglak
& &&&qq联系不上，你的报错信息不完全，感觉上是你的和谐没有和谐好造成的。64位和谐要将 ...
rabbitpan0317 发表于
& & 谢谢版主帮助，问题终于解决好了，真是和谐问题啊！
我也遇到相同的问题了，楼主是怎么解决的
QQ图片38.png (85.17 KB, 下载次数: 16)
14:43 上传
在做教程“NIOSII那些事儿-Qsys_EP4CE15”中sdram实验时，到了点击generate时遇到此问题.
环境为win7, Q2-64bit version 12.0 build 178.
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modelsim仿真Lattice的FIFO IP核出现的问题
在线时间9 小时
TA的帖子TA的资源
一粒金砂（初级）, 积分 0, 距离下一级还需 5 积分
一粒金砂（初级）, 积分 0, 距离下一级还需 5 积分
使用Lattice的ispLever软件，利用其IPexpress工具做了一个异步FIFO，并在顶层模块中成功例化，但是在用modelsim做仿真的时候，出现以下问题# ** Error: (vsim-3043) C:/Modeltech_6.2b/Lattice/Latticework/xp/DP8KA.v(116): Unresolved reference to 'GSR_INST'.# & & & & Region: /IPMC_CPU_test/IPMC_CPU/m0/pdp_ram_0_0_0/EBR_INST# ** Error: (vsim-3043) C:/Modeltech_6.2b/Lattice/Latticework/xp/DP8KA.v(117): Unresolved reference to 'PUR_INST'.# & & & & Region: /IPMC_CPU_test/IPMC_CPU/m0/pdp_ram_0_0_0/EBR_INST# ** Error: (vsim-3043) C:/Modeltech_6.2b/Lattice/Latticework/xp/FD1P3BX.v(38): Unresolved reference to 'GSR_INST'.# & & & & Region: /IPMC_CPU_test/IPMC_CPU/m0/FF_61# ** Error: (vsim-3043) C:/Modeltech_6.2b/Lattice/Latticework/xp/FD1P3BX.v(39): Unresolved reference to 'PUR_INST'.# & & & & Region: /IPMC_CPU_test/IPMC_CPU/m0/FF_61# Loading C:/Modeltech_6.2b/Lattice/Latticework.UDFDL7E_UDP_X# ** Error: (vsim-3043) C:/Modeltech_6.2b/Lattice/Latticework/xp/FD1P3DX.v(38): Unresolved reference to 'GSR_INST'.# & & & & Region: /IPMC_CPU_test/IPMC_CPU/m0/FF_60# ** Error: (vsim-3043) C:/Modeltech_6.2b/Lattice/Latticework/xp/FD1P3DX.v(39): Unresolved reference to 'PUR_INST'.# & & & & Region: /IPMC_CPU_test/IPMC_CPU/m0/FF_60类似于这样的问题还有一大串，就不贴上来了。PS：Lattice的library库文件我已经编译，仿真时也选择了该库文件。请各位大侠帮我看看，谢谢。
新的开始！
在线时间9 小时
TA的帖子TA的资源
一粒金砂（初级）, 积分 0, 距离下一级还需 5 积分
一粒金砂（初级）, 积分 0, 距离下一级还需 5 积分
顶起来，请各位帮帮忙啊，学艺不精，只好请求大家了
新的开始！
在线时间1 小时
TA的帖子TA的资源
一粒金砂（初级）, 积分 0, 距离下一级还需 5 积分
一粒金砂（初级）, 积分 0, 距离下一级还需 5 积分
我也碰到同样的问题，不知道你解决了没啊，能分享一下么
在线时间1 小时
TA的帖子TA的资源
一粒金砂（初级）, 积分 0, 距离下一级还需 5 积分
一粒金砂（初级）, 积分 0, 距离下一级还需 5 积分
问题解决了，呵呵
在测试代码上加上
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
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原帖由 wkandmary 于
17:18 发表
问题解决了，呵呵在测试代码上加上 GSR GSR_INST (.GSR(1'b1)); PUR PUR_INST (.PUR(1'b1)); 就可以了
谢谢分享 ：）
2015，继续为中国电子行业做出小小的贡献吧！
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一粒金砂（初级）, 积分 2, 距离下一级还需 3 积分
一粒金砂（初级）, 积分 2, 距离下一级还需 3 积分
你们是怎么解决的，我也做了一个，我是用里面的IP核，然后在用VHDl写了一些，想测试则这个异步FIFO的深度，就是没做出来，你们介意加我QQ吗？我想请教一下你们几位啊！我QQ：
生命贵在学习和运动！
在线时间15 小时
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一粒金砂（中级）, 积分 10, 距离下一级还需 190 积分
一粒金砂（中级）, 积分 10, 距离下一级还需 190 积分
知道为什么要加不？
在线时间1 小时
TA的帖子TA的资源
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逛了这许久，何不进去瞧瞧？verilog实现的五级流水简易CPU带板极验证
&实现一个简易的五级流水的CPU，解决Hazard，并实现板极验证。
&&& 1 设计总览
2 实现原理
根据Top view&将整个CPU分为3个模块：
&& 1 PCPU&主要模块：用从指令内存得到的指令进行运算处理，并从数据内存中写入或读取数据。这是最核心的部分，其他模块都很好设计。
&& 2 Instruction_Mem&指令模块：&为PCPU模块提供指令，使得PCPU中通过指令寄存器中的值，找到指令的内存地址，从而读取指令。
&& 3 Data_Mem&&数据模块：&PCPU从中读取数据或写入数据
板极验证：
&&&用4个开关表示选择哪一个数据显示，用4个7段数码管显示数字
3 整个PCPU的工作流程：
&五级流水：
注释：& & & &
IF&：&从指令模块中，通过指令寄存器PC寻址，获得指令。
ID：&解码指令，根据操作码提取要用到的数据输入通用寄存器。
EX：&ALU运算单元在指令的调度下，使用之前通用寄存器中的数据根据不同指令完成不同运算。运算后将结果输出到reg_C中，并设置各个标记位的值。
MEM：这里主要是针对LOAD，STORE这类的读写指令要用到的。对于其他指令没有特别要求。
WB：回写把计算结果写入指令的左值中，这里除了跳转指令和load，store指令，都是写回第一个操作数（寄存器）
4 需要实现的汇编指令
5&分阶段实现优化过程
阶段一&：&实现最基本的cpu（没有指令存储器，数据存储器，没有解决hazard，没有板极验证，什么也没有…）
&&&完成步骤：
步骤1：理解流水线工作原理
&上课时流水线是听懂了，寄存器赋值，取数这些基本原理大概弄懂了。不过实际操作还是有很多要注意的。
步骤2：开始逐级编写基本代码
&有了老师给的样例代码，整个框架基本构建好了。所以要做的就是弄清楚每个指令在每一级流水中需要做些什么，然后在每一级流水中再总结这些操作的共同点，不同点，需要特别注意的地方。
1）指令操作码的设计：
&优化：这里考虑了一下控制指令的特殊性，因为控制指令在流水每一级操作中有很大相似性，所以为了简化电路，还有判断时代码的简化，把所有控制指令的前两位设为“11”，而其他指令前两位都不是“11”。这样编写代码的时候更容易理清逻辑，综合的时候电路也简单一些。
2）指令各级流水的设计：
&这里思考了很多，设计每一条指令都需要特别小心，最重要的是在ID和EX还有ALUo中。
&&&&总结一下，主要就是整个16 bits的指令在流水线的每一步中起到“指挥”作用，然后每一级流水的工作就是在上一级完成后，利用
A &ID中的寄存器赋值：
&&& reg_A&和&reg_B中存储的是在指令右边将要送入ALU参与运算的值。
&&&由于指令的右边通常声明的是寄存器的编号（因为用户只能对通用寄存器进行操作，无法直接访问内存）或者立即数，所以要通过编号找到确定的寄存器，再将该通用寄存器里的值赋给reg_A&或者&reg_B。
优化：&这里为了减少reg_A&和&reg_B的翻转，考虑了一些优化。比如把要用到立即数的指令的立即数不写入寄存器，而是在下一级流水中之间从指令中取数。
&&B& &ex中ALUo的计算&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
主要就是用verilog本身的运算直接操作。运算后赋值个ALUo寄存器和cf标志位。
优化：比如一些用立即数的操作，之前没有存入reg_A&和&reg_B，直接从ex_ir中取数计算。
C& &mem中的读写
&&主要要和data模块进行数据传输，指令就是load和store。&
&D& wb中写回运算结果
&&&&由于算数指令和逻辑运算指令基本都是要写回到寄存器。所以这里判断为：非跳转指令，非store，load指令，则写回第一个操作数（寄存器）。
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// Create Date:
14:15:05 12/18/2014
// Design Name:
// Module Name:
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//////////////////////////////////////////////////////////////////////////////////
// data transfer & Arithmetic
`define NOP 5'b00000
`define HALT 5'b00001
`define LOAD 5'b00010
`define STORE 5'b00011
`define LDIH 5'b10000
`define ADD 5'b01000
`define ADDI 5'b01001
`define ADDC 5'b10001
`define SUB 5'b01011
`define SUBI 5'b10011
`define SUBC 5'b10111
`define CMP 5'b01100
// control
`define JUMP 5'b11000
`define JMPR 5'b11001
`define BZ 5'b11010
`define BNZ 5'b11011
`define BN 5'b11100
`define BNN 5'b11101
`define BC 5'b11110
`define BNC 5'b11111
// logic / shift
`define AND 5'b01101
`define OR 5'b01111
`define XOR 5'b01110
`define SLL 5'b00100
`define SRL 5'b00110
`define SLA 5'b00101
`define SRA 5'b00111
// general register
`define gr0
3'b000
`define gr1
3'b001
`define gr2
3'b010
`define gr3
3'b011
`define gr4
3'b100
`define gr5
3'b101
`define gr6
3'b110
`define gr7
3'b111
`define idle 1'b0
`define exec 1'b1
/* the whole module CPU is made of
Instuction_Mem module, PCPU module and Data_Mem module /
module CPU(
input wire clk, clock, enable, reset, start,
input wire[3:0] select_y,
output [7:0] select_segment,
output [3:0] select_bit
wire[15:0] d_
wire[15:0] i_
wire[7:0] d_
wire[7:0] i_
wire[15:0] d_
wire[15:0]
reg [20:0] count = 21'b0;
Instruction_Mem instruction(clock,reset,i_addr,i_datain);
PCPU pcpu(clock, enable, reset, start, d_datain, i_datain,
select_y, i_addr, d_addr, d_dataout, d_we, y);
Data_memory data(clock, reset, d_addr, d_dataout, d_we, d_datain);
Board_eval eval(clk, y, select_segment, select_bit);
/ Instruction memeory module
module Instruction_Mem (
input wire clock, reset,
input wire[7:0] i_addr,
output [15:0] i_datain
reg[15:0] i_data[255:0]; // 8 bits pc address to get instructions
always@(negedge clock)
if(!reset)
i_data[0] &= {`LOAD, `gr1, 1'b0, `gr0, 4'b0000};
i_data[1] &= {`LOAD, `gr2, 1'b0, `gr0, 4'b0001};
i_data[2] &= {`ADD, `gr3, 1'b0, `gr1, 1'b0, `gr2};
i_data[3] &= {`SUB, `gr3, 1'b0, `gr1, 1'b0, `gr2};
i_data[4] &= {`CMP, `gr3, 1'b0, `gr2, 1'b0, `gr1};
i_data[5] &= {`ADDC, `gr3, 1'b0, `gr1, 1'b0, `gr2};
i_data[6] &= {`SUBC, `gr3, 1'b0, `gr1, 1'b0, `gr2};
i_data[7] &= {`SLL, `gr2, 1'b0, `gr3, 1'b0, 3'b001};
i_data[8] &= {`SRL, `gr3, 1'b0, `gr1, 1'b0, 3'b001};
i_data[9] &= {`SLA, `gr4, 1'b0, `gr1, 1'b0, 3'b001};
i_data[10] &= {`SRA, `gr5, 1'b0, `gr1, 1'b0, 3'b001};
i_data[11] &= {`STORE, `gr3, 1'b0, `gr0, 4'b0010};
i_data[12] &= {`HALT, 11'b000_};
temp = i_data[i_addr[7:0]];
assign i_datain =
/ PCPU module */
module PCPU(
input wire clock, enable, reset, start,
input wire [15:0] d_datain,
// output from Data_Mem module
input wire [15:0] i_datain,
// output from Instruction_Mem module
input wire [3:0] select_y,
// for the board evaluation
[7:0] i_addr,
[7:0] d_addr,
[15:0] d_dataout,
reg [15:0] gr [7:0];
reg nf, zf,
reg state, next_
reg[15:0] y_
reg [15:0] id_
reg [15:0] wb_
reg [15:0] ex_
reg [15:0] mem_
reg [15:0] smdr = 0;
reg [15:0] smdr1 = 0;
reg signed [15:0] reg_C1; //有符号
reg signed [15:0] reg_A;
reg signed [15:0] reg_B;
reg signed [15:0] reg_C;
reg signed [15:0] ALUo;
//* CPU control *//
always @(posedge clock)
if (!reset)
state &= `
state &= next_
always @(*)
case (state)
if ((enable == 1'b1)
&& (start == 1'b1))
next_state &= `
next_state &= `
if ((enable == 1'b0)
|| (wb_ir[15:11] == `HALT))
next_state &= `
next_state &= `
assign i_addr = // 准备下一条指令的地址
//* IF *//
always @(posedge clock or negedge reset)
if (!reset)
id_ir &= 16'b0;
pc &= 8'b0;
else if (state ==`exec)
// Stall happens in IF stage, always compare id_ir with i_datain to decide pc and id_ir
// 当即将被执行的指令要用到之前load写入的值时， stall two stages , id and ex.
指令中后第二、三个操作数均为寄存器时，需要判断LOAD的第一个操作数是否与这些指令的后两个寄存器有冲突
为一部分算数运算指令和逻辑运算指令
if((i_datain[15:11] == `ADD
||i_datain[15:11] == `ADDC
||i_datain[15:11] == `SUB
||i_datain[15:11] == `SUBC
||i_datain[15:11] == `CMP
||i_datain[15:11] == `AND
||i_datain[15:11] == `OR
||i_datain[15:11] == `XOR)
&&( (id_ir[15:11] == `LOAD && (id_ir[10:8]
== i_datain[6:4] || id_ir[10:8]
== i_datain[2:0]))
||(ex_ir[15:11] == `LOAD && (ex_ir[10:8]
== i_datain[6:4] || ex_ir[10:8]
== i_datain[2:0]))
) // end if
id_ir &= 16'
// hold pc
指令中第二个操作数为寄存器变量并参与运算时，需要判断LOAD的第一个操作数是否与这些指令的第二个操作数的寄存器有冲突
为移位指令和STORE指令
else if (( i_datain[15:11] == `SLL
||i_datain[15:11] == `SRL
||i_datain[15:11] == `SLA
||i_datain[15:11] == `SRA
||i_datain[15:11] == `STORE)
&&((id_ir[15:11] == `LOAD &&(id_ir[10:8]
== i_datain[6:4]))
||(ex_ir[15:11] == `LOAD &&(ex_ir[10:8]
== i_datain[6:4]))
id_ir &= 16'
// hold pc
跳转指令系列，id和ex阶段都需要stall，mem阶段跳转
else if(id_ir[15:14] == 2'b11 || ex_ir[15:14] == 2'b11)
id_ir &= 16'
// hold pc
/* mem阶段跳转 */
// BZ & BNZ
if(((mem_ir[15:11] == `BZ)
&& (zf == 1'b1))
|| ((mem_ir[15:11] == `BNZ)
&& (zf == 1'b0)))
id_ir &= 16'
pc &= reg_C[7:0];
// BN & BNN
else if(((mem_ir[15:11] == `BN)
&& (nf == 1'b1))
|| ((mem_ir[15:11] == `BNN)
&& (nf == 1'b0)))
id_ir &= 16'
pc &= reg_C[7:0];
// BC & BNC
else if(((mem_ir[15:11] == `BC)
&& (cf == 1'b1))
|| ((mem_ir[15:11] == `BNC)
&& (cf == 1'b0)))
id_ir &= 16'
pc &= reg_C[7:0];
else if((mem_ir[15:11] == `JUMP)
|| (mem_ir[15:11] == `JMPR))
id_ir &= 16'
pc &= reg_C[7:0];
// 非跳转指令且没有检测到冲突
id_ir &= i_
pc &= pc + 1;
// end else
end // else reset
end // end always
//* ID *//
always @(posedge clock or negedge reset)
if (!reset)
ex_ir &= 16'b0;
reg_A &= 16'b0;
reg_B &= 16'b0;
smdr &= 16'b0;
else if (state == `exec)
//Data forwarding happens in ID stage, always check id_ir to decide reg_A/B
ex_ir &= id_
// reg_A 赋值* //
其他无冲突的情况 */
// reg_A &= r1: 要用到 r1 参与运算的指令，即除 &JUMP& 外的控制指令和一些运算指令,将寄存器r1中的值赋给reg_A
if ((id_ir[15:14] == 2'b11 && id_ir[15:11] != `JUMP)
|| (id_ir[15:11] == `LDIH)
|| (id_ir[15:11] == `ADDI)
|| (id_ir[15:11] == `SUBI))
reg_A &= gr[id_ir[10:8]];
else if (id_ir[15:11] == `LOAD)
reg_A &= gr[id_ir[6:4]];
// case for data forwarding, 当前指令第2个操作数用到之前指令第1个操作数的结果
else if(id_ir[6:4] == ex_ir[10:8])
reg_A &= ALUo;
else if(id_ir[6:4] == wb_ir[10:8])
reg_A &= reg_C1;
else if(id_ir[6:4] == mem_ir[10:8])
reg_A &= reg_C;
//reg_A &= r2: 如果运算中不用到 r1，要用到 r2， 则将 gr[r2]
reg_A &= gr[id_ir[6:4]];
//* reg_B赋值//
if (id_ir[15:11] == `STORE)
reg_B &= {12'b00, id_ir[3:0]}; //value3
smdr &= gr[id_ir[10:8]]; // r1
// case for data forwarding, 当前指令第3个操作数用到之前指令第1个操作数的结果
else if(id_ir[2:0] == ex_ir[10:8])
reg_B &= ALUo;
else if(id_ir[2:0] == wb_ir[10:8])
reg_B &= reg_C1;
else if(id_ir[2:0] == mem_ir[10:8])
reg_B &= reg_C;
其他无冲突的情况 */
((id_ir[15:11] == `ADD)
|| (id_ir[15:11] == `ADDC)
|| (id_ir[15:11] == `SUB)
|| (id_ir[15:11] == `SUBC)
|| (id_ir[15:11] == `CMP)
|| (id_ir[15:11] == `AND)
|| (id_ir[15:11] == `OR)
|| (id_ir[15:11] == `XOR))
reg_B &= gr[id_ir[2:0]];
//* ALUo *//
always @ (*)
// {val2, val3}
(ex_ir[15:11] == `JUMP)
ALUo &= {8'b0, ex_ir[7:0]};
// 跳转指令 r1 + {val2, val3}
(ex_ir[15:14] == 2'b11)
ALUo &= reg_A + {8'b0, ex_ir[7:0]};
//算数运算，逻辑运算，计算结果到ALUo， 并计算cf标志位
case(ex_ir[15:11])
`LOAD: ALUo &= reg_A + {12'b00, ex_ir[3:0]};
`STORE: ALUo &= reg_A + reg_B;
`LDIH: {cf, ALUo} &= reg_A + { ex_ir[7:0], 8'b0 };
`ADD: {cf, ALUo} &= reg_A + reg_B;
`ADDI:{cf, ALUo} &= reg_A + { 8'b0, ex_ir[7:0] };
`ADDC: {cf, ALUo} &= reg_A + reg_B +
`SUB: {cf, ALUo} &= {{1'b0, reg_A} - reg_B};
`SUBI: {cf, ALUo} &= {1'b0, reg_A }- { 8'b0, ex_ir[7:0] };
`SUBC:{cf, ALUo} &= {{1'b0, reg_A} - reg_B - cf};
`CMP: {cf, ALUo} &= {{1'b0, reg_A} - reg_B};
`AND: {cf, ALUo} &= {1'b0, reg_A & reg_B};
`OR: {cf, ALUo} &= {1'b0, reg_A | reg_B};
`XOR: {cf, ALUo} &= {1'b0, reg_A ^ reg_B};
`SLL: {cf, ALUo} &= {reg_A[4'b1111 - ex_ir[3:0]], reg_A && ex_ir[3:0]};
`SRL: {cf, ALUo} &= {reg_A[ex_ir[3:0] - 4'b0001], reg_A && ex_ir[3:0]};
`SLA: {cf, ALUo} &= {reg_A[ex_ir[3:0] - 4'b0001], reg_A &&& ex_ir[3:0]};
`SRA: {cf, ALUo} &= {reg_A[4'b1111 - ex_ir[3:0]], reg_A &&& ex_ir[3:0]};
default: begin
//* EX *//
always @(posedge clock or negedge reset)
if (!reset)
mem_ir &= 16'b0;
reg_C &= 16'b0;
smdr1 &= 16'b0;
else if (state == `exec)
mem_ir &= ex_
reg_C &= ALUo;
if (ex_ir[15:11] == `STORE)
dw &= 1'b1;
// 设置标志位zf, nf, 算数和逻辑运算
else if(ex_ir[15:14] != 2'b11 && ex_ir[15:11] != `LOAD)
zf &= (ALUo == 0)? 1:0;
nf &= (ALUo[15] == 1'b1)? 1:0;
dw &= 1'b0;
dw &= 1'b0;
// PCPU module 的输出
assign d_dataout = smdr1;
assign d_we =
assign d_addr = reg_C[7:0];
//* MEM *//
always @(posedge clock or negedge reset)
if (!reset)
wb_ir &= 16'b0;
reg_C1 &= 16'b0;
else if (state == `exec)
wb_ir &= mem_
if (mem_ir[15:11] == `LOAD)
reg_C1 &= d_
else if(mem_ir[15:14] != 2'b11)
reg_C1 &= reg_C;
//* WB *//
always @(posedge clock or negedge reset)
if (!reset)
gr[0] &= 16'b0;
gr[1] &= 16'b0;
gr[2] &= 16'b0;
gr[3] &= 16'b0;
gr[4] &= 16'b0;
gr[5] &= 16'b0;
gr[6] &= 16'b0;
gr[7] &= 16'b0;
else if (state == `exec)
// 回写到 r1
if ((wb_ir[15:14] != 2'b11)
&&(wb_ir[15:11] != `STORE)
&&(wb_ir[15:11] != `CMP)
gr[wb_ir[10:8]] &= reg_C1;
// 板极验证
assign y = y_ // 板极验证需要的输出
always @(select_y)
case(select_y)
4'b0000: y_forboard &= {8'B0,pc};
4'b0001: y_forboard &= id_
4'b0010: y_forboard &= reg_A;
4'b0011: y_forboard &= reg_B;
4'b0100: y_forboard &=
4'b0101: y_forboard &= ALUo;
4'b0110: y_forboard &= {15'b0, cf};
4'b0111: y_forboard &= {15'b0, nf};
4'b1000: y_forboard &= reg_C;
4'b1001: y_forboard &= reg_C1;
4'b1010: y_forboard &= gr[0];
4'b1011: y_forboard &= gr[1];
4'b1100: y_forboard &= gr[2];
4'b1101: y_forboard&= gr[3];
4'b1110: y_forboard &= gr[4];
4'b1111: y_forboard &= gr[5];
/ Data memory module /
Data_memory (
input wire clock, reset,
input wire [7:0] d_addr,
input wire [15:0] d_dataout,
input wire
[15:0] d_datain
reg[15:0] d_data[255:0];
always@(negedge clock) begin
if(!reset) begin
d_data[0] &= 16'hFc00;
d_data[1] &= 16'h00AB;
end else if(d_we) begin
d_data[d_addr] &= d_
end else begin
temp = d_data[d_addr];
assign d_datain =
/ Board evaluation module /
module Board_eval
input wire clock,
input wire [15:0] y,
output reg [7:0] select_segment,
output reg [3:0] select_bit
SEG_NUM0 = 8'b,
SEG_NUM1 = 8'b,
SEG_NUM2 = 8'b,
SEG_NUM3 = 8'b,
SEG_NUM4 = 8'b,
SEG_NUM5 = 8'b,
SEG_NUM6 = 8'b,
SEG_NUM7 = 8'b,
SEG_NUM8 = 8'b,
SEG_NUM9 = 8'b,
SEG_A = 8'b,
SEG_B = 8'b,
SEG_C = 8'b,
SEG_D = 8'b,
SEG_E = 8'b,
SEG_F = 8'b;
BIT_3 = 4'b0111,
BIT_2 = 4'b1011,
BIT_1 = 4'b1101,
BIT_0 = 4'b1110;
reg [20:0] count = 0;
always @ (posedge clock) begin
count &= count + 1'b1;
always @ (posedge clock) begin
case(count[19:18])
2'b00: begin
select_bit &= BIT_3;
case(y[15:12])
4'b0000: select_segment &= SEG_NUM0;
4'b0001: select_segment &= SEG_NUM1;
4'b0010: select_segment &= SEG_NUM2;
4'b0011: select_segment &= SEG_NUM3;
4'b0100: select_segment &= SEG_NUM4;
4'b0101: select_segment &= SEG_NUM5;
4'b0110: select_segment &= SEG_NUM6;
4'b0111: select_segment &= SEG_NUM7;
4'b1000: select_segment &= SEG_NUM8;
4'b1001: select_segment &= SEG_NUM9;
4'b1010: select_segment &= SEG_A;
4'b1011: select_segment &= SEG_B;
4'b1100: select_segment &= SEG_C;
4'b1101: select_segment &= SEG_D;
4'b1110: select_segment &= SEG_E;
4'b1111: select_segment &= SEG_F;
2'b01: begin
select_bit &= BIT_2;
case(y[11:8])
4'b0000: select_segment &= SEG_NUM0;
4'b0001: select_segment &= SEG_NUM1;
4'b0010: select_segment &= SEG_NUM2;
4'b0011: select_segment &= SEG_NUM3;
4'b0100: select_segment &= SEG_NUM4;
4'b0101: select_segment &= SEG_NUM5;
4'b0110: select_segment &= SEG_NUM6;
4'b0111: select_segment &= SEG_NUM7;
4'b1000: select_segment &= SEG_NUM8;
4'b1001: select_segment &= SEG_NUM9;
4'b1010: select_segment &= SEG_A;
4'b1011: select_segment &= SEG_B;
4'b1100: select_segment &= SEG_C;
4'b1101: select_segment &= SEG_D;
4'b1110: select_segment &= SEG_E;
4'b1111: select_segment &= SEG_F;
2'b10: begin
select_bit &= BIT_1;
case(y[7:4])
4'b0000: select_segment &= SEG_NUM0;
4'b0001: select_segment &= SEG_NUM1;
4'b0010: select_segment &= SEG_NUM2;
4'b0011: select_segment &= SEG_NUM3;
4'b0100: select_segment &= SEG_NUM4;
4'b0101: select_segment &= SEG_NUM5;
4'b0110: select_segment &= SEG_NUM6;
4'b0111: select_segment &= SEG_NUM7;
4'b1000: select_segment &= SEG_NUM8;
4'b1001: select_segment &= SEG_NUM9;
4'b1010: select_segment &= SEG_A;
4'b1011: select_segment &= SEG_B;
4'b1100: select_segment &= SEG_C;
4'b1101: select_segment &= SEG_D;
4'b1110: select_segment &= SEG_E;
4'b1111: select_segment &= SEG_F;
2'b11: begin
select_bit &= BIT_0;
case(y[3:0])
4'b0000: select_segment &= SEG_NUM0;
4'b0001: select_segment &= SEG_NUM1;
4'b0010: select_segment &= SEG_NUM2;
4'b0011: select_segment &= SEG_NUM3;
4'b0100: select_segment &= SEG_NUM4;
4'b0101: select_segment &= SEG_NUM5;
4'b0110: select_segment &= SEG_NUM6;
4'b0111: select_segment &= SEG_NUM7;
4'b1000: select_segment &= SEG_NUM8;
4'b1001: select_segment &= SEG_NUM9;
4'b1010: select_segment &= SEG_A;
4'b1011: select_segment &= SEG_B;
4'b1100: select_segment &= SEG_C;
4'b1101: select_segment &= SEG_D;
4'b1110: select_segment &= SEG_E;
4'b1111: select_segment &= SEG_F;
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// Create Date:
21:22:32 12/29/2014
// Design Name:
// Module Name:
C:/Users/liang/Desktop/embed/CPU/CPU/CPUTest.v
// Project Name:
// Target Device:
// Tool versions:
// Description:
// Verilog Test Fixture created by ISE for module: CPU
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
////////////////////////////////////////////////////////////////////////////////
module CPU_
reg [3:0] select_y;
// Outputs
wire [15:0]
// Instantiate the Unit Under Test (UUT)
.clock(clock),
.enable(enable),
.reset(reset),
.start(start),
.select_y(select_y)
initial begin
// Initialize Inputs
clock = 0;
enable = 0;
reset = 0;
select_y = 0;
start = 0;
// Wait 100 ns for global reset to finish
forever begin
clock &= ~
// Add stimulus here
initial begin
// Wait 100 ns for global reset to finish
$display(&pc:
cf: nf: zf:
$monitor(&%h:
%h: %h: %h:
cpu.pcpu.pc, cpu.pcpu.id_ir, cpu.pcpu.ex_ir, cpu.pcpu.reg_A, cpu.pcpu.reg_B, cpu.pcpu.reg_C,
cpu.pcpu.cf, cpu.pcpu.nf, cpu.pcpu.zf, cpu.pcpu.reg_C1, cpu.pcpu.gr[1], cpu.pcpu.gr[2], cpu.pcpu.gr[3], cpu.pcpu.gr[4], cpu.pcpu.gr[5]);
enable &= 1; start &= 0; select_y &= 0;
#10 reset &= 0;
#10 reset &= 1;
#10 enable &= 1;
#10 start &=1;
#10 start &= 0;
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