TMS320VC5507 | C55x DSP | C5000 DSP | 描述与参数
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TMS320VC5507
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定点数字信号处理器
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The TMS320VC5507 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit & 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core. The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs. The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included. The 5507 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry‘s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS51™. emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.
High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor 9.26-, 6.95-, 5-ns Instruction Cycle Time 108-, 144-, 200-MHz Clock Rate One/Two Instruction(s) Executed per Cycle Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)] Two Arithmetic/Logic Units (ALUs) Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses 64K & 16-Bit On-Chip RAM, Composed of: 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K & 16-Bit 64K Bytes of Single-Access RAM (SARAM) 8 Blocks of 4K & 16-Bit 64K Bytes of One-Wait-State On-Chip ROM (32K & 16-Bit) 8M & 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM) 16-Bit External Parallel Bus Memory Supporting Either: External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to: Asynchronous Static RAM (SRAM) Asynchronous EPROM Synchronous DRAM (SDRAM) 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities Programmable Low-Power Control of Six Device Functional Domains On-Chip Scan-Based Emulation Logic On-Chip Peripherals Two 20-Bit Timers Watchdog Timer Six-Channel Direct Memory Access (DMA) Controller Three Multichannel Buffered Serial Ports (McBSPs) Programmable Phase-Locked Loop Clock Generator Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF) USB Full-Speed (12 Mbps) Slave Port Supporting Bulk, Interrupt and Isochronous Transfers Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply 4-Channel (BGA) or 2-Channel (LQFP) 10-Bit Successive Approximation A/D IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic Packages: 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix) 179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH and ZHH Suffixes) 1.2-V Core (108 MHz), 2.7-V - 3.6-V I/Os 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os
C55x is a trademark of Texas Instruments. TMS320C55x and MicroStar BGA are trademarks of Texas Instruments. All trademarks are the property of their respective owners. (1)IEEE Standard 0 Standard-Test-Access Port and Boundary Scan Architecture.
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TMS320VC5507
Automotive
Communications and Telecom
Consumer Electronics
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1 16-bit HPI
10.27 | 1ku请问dsp各系列中，从c c6000有什么区别，那个,6000代表什么意思_百度知道
请问dsp各系列中，从c c6000有什么区别，那个,6000代表什么意思
提问者采纳
系列主要偏重于视频图像处理：2000系列主要偏重于工控领域，一般需要扩展（如6713+FPGA形式），这个系列的DSP自身集成了丰富的I&#47，多为定点型芯片;O口，性能强大，A/D采样接口及PWM输出接口，基本都为浮点型的，但自身集成的外设很少你指的的TI公司的DSP吧？这个主要是指不同系列的DSP划分
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degree 是独立使用level要配合使用
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请问dsp各系列中，从c c6000有什么区别，那个,6000代表什么意思
请问dsp各系列中，从c c6000有什么区别，那个,6000代表什么意思？TMS320VC5505 | C55x DSP | C5000 DSP | 描述与参数
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TMS320VC5505
(不推荐在新型设计中采用)
低功耗定点数字信号处理器
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不建议在新的设计中使用 (NRND)
器件与被比较器件具有相同的功能，但并不是引脚对引脚等效，也有可能参数不相同。
TI does not recommend using this part in a new design. This product continues to be in production to support existing customers.
The TMS320VC5505 is a member of TI's TMS320C5000& fixed-point Digital Signal
Processor (DSP) product family and is designed for low-power applications.
The TMS320VC5505 fixed-point DSP is based on the TMS320C55x& DSP generation CPU processor core. The C55x& DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The TMS320VC5505 also includes four DMA controllers, each with 4 channels, providing data movements for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of
17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central
40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use
of the ALUs is under instruction set control, providing the ability to optimize
parallel activity and power consumption. These resources are managed in the
Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x CPU supports a variable byte width instruction set for improved code
density. The Instruction Unit (IU) performs 32-bit program fetches from internal
or external memory and queues instructions for the Program Unit (PU). The
Program Unit decodes the instructions, directs tasks to the Address Unit (AU)
and Data Unit (DU) resources, and manages the fully protected pipeline.
Predictive branching capability avoids pipeline flushes on execution of
conditional instructions. The general-purpose input and output functions along with the 10-bit SAR ADC
provide sufficient pins for status, interrupts, and bit I/O for LCD displays,
keyboards, and media interfaces. Serial media is supported through two
MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S
Bus&) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one
I2C multi-master and slave interface, and a Universal Asynchronous
Receiver/Transmitter (UART) interface. The VC5505 peripheral set includes an external memory interface (EMIF) that
provides glueless access to asynchronous memories like EPROM, NOR, NAND, and
SRAM. Additional peripherals include: a high-speed Universal Serial Bus (USB2.0)
device mode only, and a real-time clock (RTC). The DMA controller provides data
movement for sixteen independent channel contexts without CPU intervention,
providing DMA throughput of up to two 16-bit words per cycle. This device also
includesthree general-purpose timers with one configurable as a watchdog timer,
and a analog phase-locked loop (APLL) clock generator. In addition, the VC5505 includes a tightly-coupled FFT Hardware Accelerator.
The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power
of 2) real and complex-valued FFTs. The VC5505 is supported by the industry's award-winning eXpressDSP&, Code
Composer Studio& Integrated Development Environment (IDE), DSP/BIOS&, Texas
Instruments' algorithm standard, and the industry's largest third-party network.
Code Composer Studio IDE features code generation tools including a C Compiler
and Linker, RTDX&, XDS100&, XDS510&, XDS560& emulation device drivers, and
evaluation modules. The VC5505 is also supported by the C55x DSP Library which
features more than 50 foundational software kernels (FIR filters, IIR filters,
FFTs, and various math functions) as well as chip support
High-Performance, Low-Power, TMS320C55x& Fixed-Point Digital Signal Processor
16.67-, 10-ns Instruction Cycle Time
60-, 100-MHz Clock Rate
One/Two Instruction(s) Executed per Cycle
Dual Multipliers [Up to 200 Million Multiply-Accumulates per Second (MMACS)]
Two Arithmetic/Logic Units (ALUs)
Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
Fully Software-Compatible With C55x Devices
Industrial Temperature Devices Available
320K Bytes Zero-Wait State On-Chip RAM, Composed of:
64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit)
16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
8-/16-Bit NAND Flash, 1- and 4-Bit ECC
8-/16-Bit NOR Flash
Asynchronous Static RAM (SRAM)
Direct Memory Access (DMA) Controller
Four DMA With 4 Channels Each (16-Channels Total)
Three 32-Bit General-Purpose Timers
One Selectable as a Watchdog and/or GP
Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
Universal Asynchronous Receiver/Transmitter (UART)
Serial-Port Interface (SPI) With Four Chip-Selects
Master/Slave Inter-Integrated Circuit (I2C Bus&)
Four Inter-IC Sound (I2S Bus&) for Data Transport
Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
USB 2.0 Full- and High-Speed Device
LCD Bridge With Asynchronous Interface
Tightly-Coupled FFT Hardware Accelerator
10-Bit 4-Input Successive Approximation (SAR) ADC
Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply
Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, or I2C EEPROM
IEEE-1149.1 (JTAG&) Boundary-Scan-Compatible
Up to 26 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or 3.3-V I/Os
Applications:
Wireless Audio Devices (e.g., Headsets, Microphones, Speakerphones, etc.)
Echo Cancellation Headphones
Portable Medical Devices
Voice Applications
Industrial Controls
Fingerprint Biometrics
Software Defined Radio
All trademarks are the property of their respective
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